This paper discusses the design of on-chip transformer-based fourth order filters, suitable for mm-Wave highly sensitive broadband low-noise amplifiers (LNAs) and receivers (RXs) implemented in deep-scaled CMOS. Second order effects due to layout parasitics are analyzed and new design techniques are introduced to further enhance the gain-bandwidth product of this class of filters. The design and measurements of a broadband 28-nm bulk CMOS LNA and a sliding-IF RX tailored for ${E}$ -band (i.e., 71–76-GHz and 81–86-GHz) point-to-point communication links are presented. Leveraging the proposed design methodologies, the ${E}$ -band LNA achieves a figure of merit $\approx 10.5$ -dB better than state-of-the-art designs in the same band and comparable to LNAs at lower frequencies. The RX achieves 30.8-dB conversion gain with ${E}$ -band with wide margin.

On the Design of Wideband Transformer-Based Fourth Order Matching Networks for ${E}$ -Band Receivers in 28-nm CMOS

This paper proposes a transformer-based broadband low-noise amplifier (LNA) for millimeter-wave application. The proposed LNA has four common-source stages. Three transformers are used to connect the drains of the former transistors and the sources of the following transistors to boost the transconductances of the following transistors. Thus, the gain of the circuit is effectively increased. In addition, the noise figure (NF) is decreased because the noise contributions of the following stages are further suppressed by the application of the transformers. To enhance the gain bandwidth, the gate inductor in each inter-stage matching network is independently adjusted to separate the main poles of the four stages. The LNA is demonstrated using a commercial 65-nm CMOS process. According to the measurement results, a maximum gain of 17.7 GHz at 67 GHz and a 3-dB gain bandwidth of 35.6 GHz are achieved. The measured NF is 5.4–7.4 dB at 54–67 GHz. The tested input 1-dB gain compression point (IP $_{1\,\text {dB}}$ ) ranges from −15.4 to −11.7 dBm in the entire 3-dB gain bandwidth. With 1-V power supply, the LNA consumes 19-mA dc current. The chip size is only 0.37 mm2 with all pads.

A 54.4–90 GHz Low-Noise Amplifier in 65-nm CMOS

The requirement of the fifth generation (5G) wireless communication for high throughput motivates the wireless industry to use the mmWave (millimeter wave) communications for its wide bandwidth advantage. To compensate the heavy path loss and increase the communications capacity, phased array beamforming and massive multiple-input multiple-output (MIMO) techniques are employed at both the user equipment (UE) and base stations (BS). Considering the commercial requirements, 5G mmWave large array systems should be implemented in an energy- and cost-efficient way with a small form factor. To address above issues and realize a reliable communications link, taking into account the particular characteristics of 5G mmWave systems, this paper firstly examines the design challenges and trade-offs in system implementations, then some of the design strategies are summarized. At last, recent advance in RF front-end circuits and receiver sub-systems is then highlighted.

mmWave communications for 5G: implementation challenges and advances

This paper presents the analysis and design of a novel topology of a low-noise amplifier (LNA) with gain improvement and noise reduction simultaneously. A transformer feedback ${ g}_{ m}$ -boosting technique is proposed in a single-ended cascode topology to increase the gain and reduce the noise. The proposed technique is theoretically formulated and detailed analyses are presented. Two V-band single-ended cascode LNAs, with a transformer and transmission line for impedance matching, respectively, are demonstrated to verify this technique. Fabricated in a 65-nm CMOS process, the transformer-based (TF-based) LNA exhibits a minimum noise figure (NF) of 3.6 dB at 53.5 GHz and a highest power gain of 28.2 dB at 54 GHz in measurement. To our best knowledge, this LNA has the best NF and power gain among all the published V-band LNAs in 65-nm CMOS up to date. The transmission-line-based (TL-based) LNA exhibits a minimum NF of 3.8 dB at 53.9 GHz and a highest power gain of 25.4 dB at 54.2 GHz in measurement. Both the LNAs consume 18 mA from a power supply of 1.1 V.

A Transformer Feedback ${G}_{m}$ -Boosting Technique for Gain Improvement and Noise Reduction in mm-Wave Cascode LNAs

How to make key 5G wireless technologies environmental friendly: A review

A current-mode 60-GHz direct-conversion receiver, which can break performance tradeoffs among bandwidth, noise figure (NF), and linearity is designed and realized in 65-nm CMOS. The 60-GHz receiver employs the novel frequency-staggered series resonance common source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receiver's current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature local oscillator generations, the fabricated receiver simultaneously achieves minimal NF of 3.8 dB, RF bandwidth of 7.5 GHz, output ${ P}_{1\ {\rm dB}}$ of 1 dBm, and maximum conversion gain of 36 dB. The receiver is capable of tolerating out-of-channel blocker up to $-$ 9 dBm at 3.5 GHz away. It occupies a silicon area of 1.3 ${\hbox{mm}}^{2}$ and draws 25.5 mA of current from a 1-V supply.

A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS

A current-mode mm-wave direct-conversion receiver breaking trade-offs among bandwidth, NF and linearity is designed and realized in 65nm CMOS. The 60GHz receiver employs novel Frequency-staggered Series Resonance Common Source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receiver's current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature LO generations, the fabricated receiver simultaneously achieves minimal noise figure of 3.8dB, RF bandwidth of 7.5GHz, output P1dB of 1dBm, maximum conversion gain of 32dB, and IRR of -35dB. The receiver is capable of tolerating outof-channel blocker up to -9dBm at 3.5GHz away. It occupies silicon area of 1.3mm2 and draws 25.5mA from 1V supply.

A Current-Mode mm-Wave direct-conversion receiver with 7.5GHz Bandwidth, 3.8dB minimum noise-figure and +1dBm P 1dB, out linearity for high data rate communications

A direct conversion receiver which consists of low noise amplifier (LNA), mixer and programmable gain amplifier (PGA) for V-band (60GHz) applications is designed and realized in 65nm CMOS. A novel two-dimensional passive g m -enhancement technique is devised to boost the conversion gain and lower the Noise Figure (NF) with insignificant power overhead. An overall minimum SSB NF of 3.9dB and a maximum power conversion gain of 60dB have been validated from such fabricated receiver that occupies core silicon area of 0.2mm2 and draws 34mA from 1V supply.

Ning-Yi Wang

Papers

A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS

A Current-Mode mm-Wave direct-conversion receiver with 7.5GHz Bandwidth, 3.8dB minimum noise-figure and +1dBm P 1dB, out linearity for high data rate communications

A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive G m -enhancement