Sung-Geun Do

TL;DR: This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process and introduces a dual channel for a data granularity of 32B with a BL16, per-bit training of l/REF, and an equalizer with PLL-less clocking.

TL;DR: A 2Gb LPDDR4 SDRAM with 0.15mW standby mode power is presented, which is 66% lower than the standby power for a memory of the same density and achieves a bandwidth of 3.733Gb/s/pin.

TL;DR: This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process.

TL;DR: This paper has successfully implemented a 9.5Gb/s/pin 16Gb LPDDR5X using a fourth generation 10nm DRAM fabrication technology and has new high-speed enabling features: per-pin DFE training, pre-emphasis for DQ driver, receiver offset calibration training, and a read duty-cycle adjuster.