Showing papers by "Peter Hazucha published in 2004"

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

Abstract: We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop with only 2.5 nF of on-chip decoupling, for 0.5 A of load current. No off-chip decoupling was connected to the output. At 480 MHz the measured efficiency was 72%. At 250 MHz, the efficiency improved to 76% at the cost of a 17% droop or larger decoupling of 11.5 nF. A converter with 100 A rating would require a capacitor of 0.5 /spl mu/F, which is comparable to the size of an on-chip capacitor of a typical microprocessor.

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

Abstract: We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Abstract: Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

Cpu power delivery system

Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.

An area-efficient, integrated, linear regulator with ultra-fast load regulation

Abstract: We demonstrate a fully-integrated linear regulator for multi-supply-voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast, single-stage load regulation achieves 0.54 ns response time at 94% current efficiency. This enables 10% peak-to-peak output noise for a 100 mA load step with only a small on-chip decoupling capacitor of 0.6 nF. A PMOS pull-up transistor in the output stage results in a small regulator area of 0.008 mm/sup 2/ and the 0.6 nF MOS capacitor area of 0.090 mm/sup 2/.

Magnetic material for transformers and/or inductors

Abstract: A transformer is provided that includes a plurality of metal lines and a magnetic material provided about the plurality of metal lines. The magnetic material may include a structure to reduce Eddy currents flowing in the magnetic material. This structure may be a plurality of slots extending perpendicular to the metal lines. This structure may also be a laminated structure.

Power management integrated circuit

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Power delivery system

Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.

Systems, multiphase power converters with droop-control circuitry and methods

Abstract: Droop-control circuitry of a multiphase power converter determines when multiphase switching signals are concurrently at either a high or low state and temporarily clamps the output of the power converter to either a high or low voltage level in response thereto.

Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops

Abstract: Soft error rate measurements for flip-flops on two testchips in 180nm and 130nm logic technologies show that using forward body bias improves alpha SER by 35% and neutron SER by 23%, while applying reverse body bias degrades SER by 9% to 36%. Body bias impact on SER remains virtually unchanged with technology scaling.

Clock and data recovery circuit

Abstract: A clock and data recovery circuit is provided that includes a phase/frequency detector to receive input data and multiphase clock signals. The phase/frequency detector including a first set of flip-flop circuits each to sample the input data at one of the multiphase clock signals and each to output a sampled data, and a second set of flip-flop circuits to retime the sampled data based on a similar clock signal applied to each of the second set of flip-flop circuits.

High-speed, dual-loop push-pull voltage regulator

Abstract: A series voltage regulator circuit includes first and second voltage regulators, a first controller to control an output voltage of the first voltage regulator, and a second controller to control an output voltage of the second voltage regulator. The voltage regulators preferably include internal control loops which rapidly respond to the load variations, however the controllers operate independently from these variations. By isolating the controllers from the load, the controllers are able to maintain the output of the regulators at a constant value. In one embodiment, the voltage regulators are connected in a push-pull configuration for driving the load.

DC/DC converters using dynamically-adjusted variable-size switches

Abstract: DC/DC converters using dynamically adjusted variable size switches are described herein. In one embodiment, a power switch includes multiple switching elements coupled to each other, each of the switching elements independently switching to convert an input voltage to an output voltage of a DC/DC converter, and a duty cycle of the DC/DC converter being determined based on a duty cycle of each of the switching elements. Other methods and apparatuses are also described.

On-die micro-transformer structures with magnetic materials

Abstract: A transformer integrated on a die, the transformer comprising a set of conductive lines (302) formed on the die within one layer and interconnected among each other so that no two lines belonging to any one winding are nearest neighbors. The set of conductive lines (302) is surrounded by a magnetic material (304), which may be amorphous CoZrTa, CoFeHfO, CoAlO, FeSiO, CoFeAlO, CoNbTa, CoZr, and other amorphous cobalt alloys. The transformer may be operated at frequencies higher than 10 MHz and as high as 1 GHz, with relatively low resistance and relatively high magnetic coupling between the windings.

Resonance suppression circuit

Abstract: A resonance suppression circuit is provided to suppress resonance on a power grid of a chip or die. The resonance suppression circuit may include a band-pass filter portion, a comparator portion, an amplification portion and a current dissipation portion. The band-pass filter portion may include an inverter coupled between two signal lines of the power grid. The comparator portion may sense voltage fluctuations at approximately the resonance frequency and trigger the current dissipation portion to turn ON and thereby change the frequency spectrum of the load current on the power grid to suppress the power grid resonance.

A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS

Abstract: We demonstrate an integrated buck DC-DC converter implemented in a 90nm CMOS technology for multi-Vcc microprocessors. High switching frequency (100-317MHz), 4-phase topology, and fast hysteretic control reduce inductor and capacitor sizes by 1000x, thereby enabling off-chip inductors with no magnetic core and an on-chip decoupling capacitor. The converter achieves 80-87.7% efficiency and 10% peak-to-peak output noise.

Stepwise drivers for DC/DC converters

Abstract: Stepwise drivers for DC/DC converters are described herein. In one embodiment, a stepwise driver is provided to charge or discharge a gate capacitance of a power switch of a DC/DC converter. In a particular embodiment, a stepwise driver example includes multiple switching elements to sequentially switch to charge a gate capacitance of a power switch of a DC/DC converter from a first voltage to a second voltage in multiple steps. Other methods and apparatuses are also described.

Method and apparatus for measuring coil current

Abstract: A method is described that comprises flowing current from one region of a coil to another region of the coil. The flowing induces—through flux linkage—a voltage across a second coil. A second current substantially does not flow through the second coil. The method also includes measuring the current with a first voltage at the another region of the coil and a second voltage at the second coil.

Power delivery system in which power supply and load exchange power consumption measurements via digital bus

Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.