Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ ${{\mu }}$ m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Tunnel Field-Effect Transistors: State-of-the-Art

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

A comprehensive review on emerging artificial neuromorphic devices

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

The discovery of ferroelectricity in oxides that are compatible with modern semiconductor manufacturing processes, such as hafnium oxide, has led to a re-emergence of the ferroelectric field-effect transistor in advanced microelectronics. A ferroelectric field-effect transistor combines a ferroelectric material with a semiconductor in a transistor structure. In doing so, it merges logic and memory functionalities at the single-device level, delivering some of the most pressing hardware-level demands for emerging computing paradigms. Here, we examine the potential of the ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models. We highlight the material- and device-level challenges involved in high-volume manufacturing in advanced technology nodes (≤10 nm), which are reminiscent of those encountered in the early days of high-K-metal-gate transistor development. We argue that the ferroelectric field-effect transistors can be a key hardware component in the future of computing, providing a new approach to electronics that we term ferroelectronics. This Perspective examines the use of ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models, arguing that the devices will be a key component in the development of data-centric computing.

The future of ferroelectric field-effect transistor technology

In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high- $k$ dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high $I_{{\rm ON}}/I_{{\rm OFF}}$ ratio $(\sim 6\times 10^{8})$ , a point subthreshold slope (SS) of ${\sim}{\rm 38}~{\rm mV}$ /decade, and an average SS of ${\sim}{\rm 70}~{\rm mV}$ /decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.

Junctionless Tunnel Field Effect Transistor

The invention provides a tunneling field effect transistor and a preparation method thereof, which belongs to the field of tunneling field effect transistor (TFET) logic devices and circuits in CMOS (Complementary Metal-Oxide-Semiconductor Transistor) ultra large scale integrated (ULSI) circuits. The core of the invention is that: for an N type transistor, P is injected into one side of a doping source region close to the edge of a control grid on the basis of N doping, so that the original N doping of an injected part is completely compensated as P ; and for a P type transistor, N is injected into one side of the doping source region close to the edge of the control grid on the basis of P doping, so that the original P doping of the injected part is completely compensated as N . In the structure of the device, doping injection of two different concentrations is performed in the source region, so that the characteristic of large conducting current of an MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) is combined effectively, the on-state current of the device is increased, and threshold value adjustment of MOSFET and TFET parts of the device is realized in a self-adaptive way.

Self-adaptive composite mechanism tunneling field effect transistor (TFET) and preparation method thereof

Magneto-electronic logic is an innovative approach to performing high-efficiency computations. Additionally, the ultra-large scale integration requirement for computation strongly suggests exploiting magnetoresistance effects in non-magnetic semiconductor materials. Here, we demonstrate the magnetoresistance effect in a silicon nanowire field effect transistor (SNWT) fabricated by complementary metal-oxide-semiconductor (CMOS)-compatible technology. Our experimental results show that the sign and the magnitude of the magnetoresistance in SNWTs can be effectively controlled by the drain-source voltage and the gate-source voltage, respectively, playing the role of a multi-terminal tunable magnetoresistance device. Various current models are established and in good agreement with the experimental results that describe the impact of electrical voltage and magnetic field on magnetoresistance, which provides design feasibility for the high-density magneto-electronic circuit. Such findings will further pave the way for nanoscale silicon-based magneto-electronics logic devices and show a possible path beyond the developmental limits of CMOS logic.

/pdf/voltage-controlled-magnetoresistance-in-silicon-nanowire-2qrolmcqu7.pdf

Voltage-Controlled Magnetoresistance in Silicon Nanowire Transistors

In this work, the transient response of a novel Negative Capacitance Tunnel FET (NC-TFET) design is experimentally studied under different sweeping rates of gate input voltage. Within a range of sweeping rate, the transient device characteristics exhibit improved subthreshold swing compared with DC results, which experimentally clarifies that the voltage amplification caused by NC effect is derived from the ferroelectric polarization switching rather than the stabilized switching process. Moreover, the measured transient results further indicate that the hysteresis of NC-based devices is also generated from the FE inherent dynamic behavior, and can be reduced under relatively low sweeping rate. This work provides new understanding and corresponding experimental evidence for NC effect.

Experimental Study on the Transient Response of Negative Capacitance Tunnel FET

Energy efficiency has become the main concern of IC technology. Tunnel FET (TFET) is recognized to possess the superiority of energy efficiency over MOSFET at ultralow voltage, while variability might limit the voltage reduction and thus the energy saving. Recently, device source doping gradient (SDG) is found to be the dominant variation source in TFET. In this paper, for the first time, with the awareness of SDG variation, the energy efficiency of TFET-based circuits with different activity factors ( $\alpha $ ) is comprehensively reassessed and the device optimization strategy is provided. It is found that the superiority of energy efficiency of TFET will significantly decrease especially for the more active circuit due to the inherent tradeoff between SDG variation and nominal SDG. Based on the quantitative relationship between SDG variation and nominal SDG extracted from the experimental devices, the optimal design of tunnel junction abruptness to maximize the circuit energy efficiency is obtained, leading to significant energy efficiency improvements of TFET-based circuit over MOSFET even for circuit with high $\alpha $ . This paper provides helpful device design guidelines for TFET with device variability awareness from the perspective of circuit energy efficiency.

New Insights Into Energy Efficiency of Tunnel FET With Awareness of Source Doping Gradient Variation

Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

Qianqian Huang

Papers

Self-adaptive composite mechanism tunneling field effect transistor (TFET) and preparation method thereof

Voltage-Controlled Magnetoresistance in Silicon Nanowire Transistors

Experimental Study on the Transient Response of Negative Capacitance Tunnel FET

New Insights Into Energy Efficiency of Tunnel FET With Awareness of Source Doping Gradient Variation

Method for fabricating complementary tunneling field effect transistor based on standard CMOS IC process