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Qianqian Huang
Researcher at Peking University
Publications - 150
Citations - 1327
Qianqian Huang is an academic researcher from Peking University. The author has contributed to research in topics: Transistor & Field-effect transistor. The author has an hindex of 15, co-authored 127 publications receiving 964 citations. Previous affiliations of Qianqian Huang include Information Technology Institute.
Papers
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Journal ArticleDOI
Vertical WS 2 /SnS 2 van der Waals Heterostructure for Tunneling Transistors
Jiaxin Wang,Rundong Jia,Qianqian Huang,Chen Pan,Jiadi Zhu,Huimin Wang,Cheng Chen,Yawen Zhang,Yuchao Yang,Haisheng Song,Feng Miao,Ru Huang +11 more
TL;DR: The optimal 2D-2D heterostructure for tunneling transistors is presented and elaborately engineered, taking into consideration both electric properties and material stability, and can guide possible development of energy-efficient future-generation electronics.
Proceedings ArticleDOI
First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap
Qianqian Huang,Rundong Jia,Cheng Chen,Zhu Hao,Lingyi Guo,Junyao Wang,Jiaxin Wang,Chunlei Wu,Runsheng Wang,Weihai Bu,Jing Kang,Wenbo Wang,Hanming Wu,Shiuh-Wuu Lee,Yangyuan Wang,Ru Huang +15 more
TL;DR: In this paper, complementary tunnel-FETs (C-TFETs) are integrated with CMOS foundry for high volume production, demonstrating an intrinsic tradeoff between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs.
Journal ArticleDOI
A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ Ratio
Yang Zhao,Chunlei Wu,Qianqian Huang,Cheng Chen,Jiadi Zhu,Lingyi Guo,Rundong Jia,Zhu Lv,Yuchao Yang,Ming Li,Ru Huang +10 more
TL;DR: A novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized for the first time, which can effectively suppress the sub-threshold slope (SS) degradation without leakage current increase through self-adaptively current replenishing with bandgap engineering, greatly alleviating the critical issue of high average SS in conventional TFETs.
Journal ArticleDOI
Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior
TL;DR: In this article, a design guideline for complementary heterostructure tunnel FETs is proposed based on the insight into the tradeoff between n-type and p-type HTFETs optimization.
Journal ArticleDOI
Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling
TL;DR: The surface-potential-based current model is established which is in a good agreement with TCAD simulation results and a new calculation method for the dynamic tunneling width is derived from the surface potential.