Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ ${{\mu }}$ m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Tunnel Field-Effect Transistors: State-of-the-Art

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

A comprehensive review on emerging artificial neuromorphic devices

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

The discovery of ferroelectricity in oxides that are compatible with modern semiconductor manufacturing processes, such as hafnium oxide, has led to a re-emergence of the ferroelectric field-effect transistor in advanced microelectronics. A ferroelectric field-effect transistor combines a ferroelectric material with a semiconductor in a transistor structure. In doing so, it merges logic and memory functionalities at the single-device level, delivering some of the most pressing hardware-level demands for emerging computing paradigms. Here, we examine the potential of the ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models. We highlight the material- and device-level challenges involved in high-volume manufacturing in advanced technology nodes (≤10 nm), which are reminiscent of those encountered in the early days of high-K-metal-gate transistor development. We argue that the ferroelectric field-effect transistors can be a key hardware component in the future of computing, providing a new approach to electronics that we term ferroelectronics. This Perspective examines the use of ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models, arguing that the devices will be a key component in the development of data-centric computing.

The future of ferroelectric field-effect transistor technology

In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high- $k$ dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high $I_{{\rm ON}}/I_{{\rm OFF}}$ ratio $(\sim 6\times 10^{8})$ , a point subthreshold slope (SS) of ${\sim}{\rm 38}~{\rm mV}$ /decade, and an average SS of ${\sim}{\rm 70}~{\rm mV}$ /decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.

Junctionless Tunnel Field Effect Transistor

In this letter, a novel negative capacitance tunnel FET (NC-TFET) design based on junction depleted-modulation is proposed and experimentally demonstrated with sub-60mV/dec subthreshold swing (SS). By a striped gate stack design with integrated ferroelectric Hf0.5Zr0.5O2, the fabricated Si NC junction-modulated TFET (NC-JTFET) exhibits steeper SS, higher ON-current for almost two decades than Si TFET without OFF-current degradation, as well as nearly non-hysteresis behavior. The experimental results show the great potential of NC-JTFET for ultralow-standby-power IoT applications.

A Novel Negative Capacitance Tunnel FET With Improved Subthreshold Swing and Nearly Non-Hysteresis Through Hybrid Modulation

In this letter, a Schottky barrier impact-ionization metal-oxide-semiconductor (SB-IMOS) device with reduced operating voltage is proposed and investigated. By introducing the silicide source and combining impact ionization with Schottky barrier tunneling, source parasitical resistance can be extremely reduced and the device performance can be improved. The device is optimized with Schottky barrier height variation additionally. Both SB-IMOS and conventional impact-ionization metal-oxide-semiconductor devices were fabricated using the standard complementary metal-oxide-semiconductor technology. SB-IMOS exhibits a 33% lower operating voltage, 43% lower threshold voltage, and improvement of ON current by 2 orders of magnitude while maintaining steep subthreshold swing of 10.2 mV/dec.

Schottky barrier impact-ionization metal-oxide-semiconductor device with reduced operating voltage

In this letter, a novel graded-channel heterojunction tunnel field-effect transistor (GCH-TFET) is proposed and studied by simulation. The novel TFET adopts a near broken-gap heterojunction at the source/channel interface to enhance the tunnel efficiency. Besides, it employs a graded component channel which works as an electron barrier to block up the leakage current at the OFF-state and can be removed with the increased gate voltage at the ON-state for high ON/ OFF-current ( ${I}_{\scriptscriptstyle\text {ON}}/{I}_{\scriptscriptstyle\text {OFF}}$ ) ratio. Such graded channel also allows a sudden turn-on of band-to-band tunneling, resulting in a reduced sub-threshold swing (SS) compared with conventional heterojunction TFETs. The GCH-TFET demonstrates an ${I}_{\scriptscriptstyle\text {ON}}/{I}_{\scriptscriptstyle\text {OFF}}$ ratio of more than seven decades with ${I}_{\scriptscriptstyle\text {ON}}$ up to 225 $\mu \text{A}/\mu \text{m}$ at ${V}_{\textsf {DD}} = \textsf {0.3}$ V, ${I}_{\scriptscriptstyle\text {OFF}}$ more than two decades lower than a near broken-gap heterojunction TFET and SS lower than 30 mV/decade for more than five decades, exhibiting excellent potential for ultra-low power applications.

Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing

The low frequency noise (LFN) mechanisms of TFETs with different source junction design are experimentally studied for the first time, including the random telegraph signal (RTS) noise. Different from MOSFET, due to the non-local band-to-band tunneling (BTBT) mechanism and small LFN-generating area, both 1/f and 1/f 2 LFN dependence can be observed in large TFETs with large device to device variability, as well as high noise. It is found that the “active” traps responsible for the noise mechanism are located in the area where electron-hole pairs generated by non-local BTBT, and the trap located at the maximum junction electric field tends to have relatively weak impacts on the TFET noise. With new abrupt tunnel junction design, it is observed that the device variability can be effectively alleviated with much lower noise level. In addition, a single-trap-induced RTS noise in TFETs with different source junction design is also experimentally investigated. New features, including strong V D dependence of RTS parameters and significantly high amplitude (~28%), indicate the desirable requirement for the source junction optimization in TFETs.

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering

In this paper, we propose a machine-learning assisted modeling framework in design-technology co-optimization (DTCO) flow. Neural network (NN) based surrogate model is used as an alternative of compact model of new devices without prior knowledge of device physics to predict device and circuit electrical characteristics. This modeling framework is demonstrated and verified in FinFET with high predicted accuracy in device and circuit level. Details about the data handling and prediction results are discussed. Moreover, same framework is applied to new mechanism device tunnel FET (TFET) to predict device and circuit characteristics. This work provides new modeling method for DTCO flow.

Qianqian Huang

Papers

A Novel Negative Capacitance Tunnel FET With Improved Subthreshold Swing and Nearly Non-Hysteresis Through Hybrid Modulation

Schottky barrier impact-ionization metal-oxide-semiconductor device with reduced operating voltage

Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering

New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework