Showing papers by "Rao Tummala published in 2003"

Polymer-ceramic nanocomposite capacitors for system-on-package (SOP) applications

Abstract: This work focuses on optimizing the dispersion of nanosized ceramic particles for achieving higher dielectric constant, thereby higher capacitance density in polymer/ceramic nanocomposites. It has been observed that high solids loading leads to entrapment of porosity in the microstructure which lowers the effective dielectric constant of the films. The amount of solvent in the suspension and the speed at which spin coating was performed were found to impact the dielectric constant of high filler content nanocomposites. The interplay between the rheological properties of the suspension and processing parameters such as solvent content and coating speeds and its impact on the dielectric properties of the film are discussed. Porosity of thin film composites was measured for the first time to study the impact of these processing parameters. Powders of different particle sizes were mixed to obtain bimodal particle size distribution in order to increase the packing density of the composite. Packing density was improved by modifying the dispersion methodology. A nanocomposite with dielectric constant as high as 135 was obtained for the first time in the low-cost printed wiring board compatible epoxy system. A capacitance densities of /spl sim/35 nF/cm/sup 2/ on a nominal 3.5 micrometer films was achieved on PWB substrates with high yield. The manufacturability of these formulated nanocomposites and their applications as decoupling capacitors have been tested using a large area (300 mm /spl times/ 300 mm) system-on-package (SOP) chip-to-chip communication test vehicle.

Electrical design of wafer level package on board for gigabit data transmission

Abstract: This paper discusses the design of a wafer level package on board for 5GHz data transmission. The design is based on the 2005 node of the International Technology Roadmap on Semiconductors (ITRS) that predicts a clock frequency of 5GHz, power of 170W and an operating voltage of 0.9V for high-end microprocessors. The goal of this paper is to demonstrate the ability to support global interconnections on the board at a speed comparable to the clock frequency and supply adequate power to the chip. This requires careful design of the topology of the interconnections, control of the eddy current losses in Silicon, control of the conductor and dielectric losses in the board and design of the transition between the chip and the board. The electrical design process is discussed in detail using a test vehicle, in this paper. The test vehicle consists of Co-planar waveguide (CPW) lines on high resistivity Silicon Substrate connected to CPW lines on low k, low loss board. The transition between the chip and board is completed through solder bumps with 50 /spl mu/m diameter and 100 /spl mu/m pitch. Both the Silicon and Board transmission lines have been characterized using TDR measurements. In addition, the inductance of the solder bumps have been extracted. Using synthesized models extracted from measurements, the eye diagrams for 5GHz data transmission has been simulated to show the importance of losses for 1mm long Silicon lines connected to 5cm long board lines through low inductance solder bumps. In addition, the effect of underfill and curing on signal propagation have been quantified.

A novel technology for stacking microvias on printed wiring board

Abstract: A novel stacked microvia technology is being developed by the Packaging Research Center (PRC) at the Georgia Institute of Technology for system-on-a package (SOP) applications. This ultra-high density build-up multilayer technology uses low cost processes to fabricate stacked microvias of non-conformal copper studs with uniform height on organic printed wiring boards. This process involves the use of copper panel plating and selective etch back using a protective or barrier layer to protect the underlying circuit traces. We have termed this new process PES (Panel Plating Etch Stud). Stacked via technology offers higher wiring capability and improved performance compared with conventional conformal microvias used for high density interconnect (HDI) boards. This paper will review the current statns of via filling technologies for stacked vias and descrihe the new P'ES process along with preliminary results. In addition, the PRC is also developing ultra fme circuit lines and spaces on printed circuit boards. The use of stacked vias along with ultra fme line technology will dramatically reduce size and increase performance of electronic systems.

Low temperature sintering process for deposition of nano-structured metal for nano IC packaging

Abstract: This paper presents the study of some nano-sized metal powders, and the processes of depositing these on silicon wafers, for use in nano-structured wafer level interconnects. Nano-powders, /spl sim/50-100 nm, of copper and silver, obtained by electro-explosion of the metal wire, are used in this study. Pastes were obtained by suspension of the nano metallic powder in surfactants, organic carriers and reducing agents. The pastes were printed onto surface-treated silicon wafers and sintered at around 400/spl deg/C. Results show that there is a potential of lowering the sintering temperature to 200/spl deg/C, which would be more ideal for microelectronics applications.

Advances in fine pitch lead free assembly process

Abstract: This research focuses on evolving the best possible criteria for selecting high electrical performance 100 micron pitch lead free solder bumping process This is achieved through modeling and simulating the pad, process, reliability and test strategy Coplanar waveguides (CPW) were modeled to evolve process criteria for pad design and choice of materials Polyimide was chosen as the passivation on the chip Further signal parasitics were studied for the passivation and a selection criterion was evolved for its thickness The pad and the passivation layers were studied for dielectric loss when subjected to thermal cychg (air to ai) This evaluation leads to the selection of the hest pad contigumtion for lead free solder An in-depth study on how internal resistance of the solder contributes to the change in parasitics is presented through numerical and simulated models Standard under hump metallurgy (UBM) was used on the pads Lead free solder (Sn35Ag03Cu) was chosen as the bumping material Bumping strategy was evolved by which solder can be deposited on the UBM without stencil printing or electroplating Flip chip B-stage underfill was also evaluated for wafer level application and standardized This paper concludes by suggesting the hest design, process and reliability criteria which should be adopted for lead free solder 100 pm pitch flip-chip Iutroductiou

In-situ stress and warpage measurements to investigate reliability of flip-chip on board assembly without underfill

Abstract: Current printed wiring boards (PWBs) are all organic, the most common being epoxy-glass laminate FR-4 due to its cost effectiveness and overall perfonnance. However, for highdensity wiring (HDW) and assembly of flip-chips directly to the substrate without the use of underfill, substrate materials with low CTE and high elastic modulus are needed. Novel low CTE-high stiffness organic and inorganic hoards have been evaluated for flip-chip on board technology without the use of underfill. Standard liquid-liquid thermal shock tests were carried out on test vehicles with different board materials and failure modes were characterized. In-situ warpage and stress measurements were made to analyze the observed failure modes and to set guidelines for optimal board material selection. The effect of interlayer dielectric thickness on the package reliability has also been studied. The reliability test results are in accordance with the inferences from the in-situ warpage and stress measurements and it can be concluded that along with low CTE, high modulus is an inevitable substrate property requirement for flip-chip reliability without underfill in next-generation packages. This paper also presents Photostimulated Luminescence Spectroscopy (PSLS) and Raman Spectroscopy as non-destructive and direct techniques for the in-situ and residual stress measurement in microsystems and thus a powerful means for reliability assessment. Experimental results have also been supported by finite element models and analytical solutions.

Meniscus coating: a low-cost polymer deposition method for system-on-package (SOP) substrates

Abstract: Meniscus coating is a low-cost deposition method that can be used to apply polymers in solution as thin films to the surface of electronics packaging substrates or flat panel displays. Most Roadmaps in electronics packaging project 6 to 8 /spl mu/m lines and spaces for next generation high density printed wiring board (PWB) substrates in the year 2006, which would require coating thickness of similar magnitudes for manufacturing fine lines with higher yield. Meniscus coating can be an enabling deposition method that can provide finer yet uniform coating on large area substrates which would translate to patterning finer copper traces, thereby increasing the wiring density. This paper reports preliminary results on coating thickness that can be achieved with photoresists, dielectrics, and solder masks which are the integral parts of the sequential build up multi-layer process for the system-on-package substrates.

Integration and high-frequency characterization of PWB-compatible pure barium titanate films synthesized by modified hydrothermal techniques (< 100/spl deg/C)

Abstract: This work reports synthesis of pure Barium Titanate films on Printed Wiring Board at temperatures less than 10v C using hydrothermal synthesis technique. The films thus synthesized were found be crystalline with gain size of 80100 nm. The film thickness was found to be 300 nm and the capacitance density was in the order of 1 pF/cm*, resulting in a dielectric constant of 400. Films grown on thiier Ti foils (42 microns) showed almost 100 % yield. High frequency dielectric properties were obtained from s-parameter measurements using a multi-line calibration approach and were found to be stable up to 8 GHz. Low-cost and low temperature synthesis and stable dielectric properties in the GHz frequencies make them ideal candidates for integral capacitor applications.

New package/board materials technology for next-generation convergent microsystems

Abstract: Current printed wiring boards (PWBs) are all organic, the most common being epoxy-glass laminate FR-4 due to its cost effectiveness and overall performance However, for high-density wiring (HDW) and assembly of flip-chips directly to the substrate without the use of underfill, substrate materials with low CTE and high elastic modulus are needed Novel low CTE-high stiffness organic (carbon-epoxy) and inorganic boards (carbon-SiC) have been evaluated for flip-chip on board technology without the use of underfill Standard liquid-liquid thermal shock tests were carried out on test vehicles with different board materials In-situ warpage measurements and optical microscopy were used to analyze the observed failure modes The low CTE low stiffness ceramic and organic boards did not fail from solder joint failure but from cracking in the dielectrics and copper wiring The high stiffness (>350 GPa) ceramic boards did not fail even after 1000 cycles The failure modes indicate that a combination of high dielectric stresses and warpage results in crack propagation in conventional epoxies The novel high stiffness low-CTE ceramic (C-SiC) is also processable in large-area at low cost and is hence a promising board material for future microsystems

Ultra-high density board technology for sub-100 /spl mu/m pitch nano-wafer level packaging

Abstract: As microsystems continue to move towards higher speed and microminiaturization, the demand for interconnection density both on the IC and the package increases tremendously With the shift towards nano ICs by 2004 with <100 nm feature sizes, the area array I/O pitch will move towards 20-100 micron in the future The 2002 ITRS Roadmap Update identifies the need to support sub-100 /spl mu/m pitch flip-chip/WLP and data rates of 10Gbps in the package and board by the year 2010 The PRC and IME/NUS are developing 20-100 /spl mu/m pitch interconnects as part of the A*STAR nano-WLP program A critical part of this development involves board technology to simultaneously support wiring density to direct attach of these WLPs and high speed signals The choice of base substrate and thin film dielectric is critical to meet the electrical performance targets and achieve reliable assembly of fine pitch WLPs Modeling revealed that a low CTE substrate greatly enhances the reliability of all the interconnect solutions being pursued The fabrication process was done on 300 mm /spl times/ 300 mm and 300 mm /spl times/ 450 mm panel sizes using state-of-the-art printed wiring board and microvia processes Data rates of 5Gbps on board have been demonstrated for line lengths of 10 cm using A-PPE dielectric Fine pitch routing using 20 /spl mu/m lines and spaces on Hitachi E-679F low CTE laminate to support 200 /spl mu/m pitch pads have been demonstrated Initial substrates for 100 /spl mu/m pitch have also been designed and fabricated

Sol-gel derived and repairable nano-interconnects

Abstract: Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. There is definitive evidence that nano-structured interconnects can provide better resistance to crack growth and fatigue resistance and hence improve mechanical reliability without sacrificing the electrical properties. Current approaches to interconnects such as reflowed solder paste and electroplated interconnects cannot easily achieve nano-grained structures and also impose restrictions on the processibility. For example, screen-printing solder pastes cannot achieve very fine pitches, while electroplated interconnects are restricted to a few material systems. The current wafer level packages are at a pitch of 250-400 microns. We propose solution derived reworkable nano-interconnects as a viable technology to meet the needs of reducing pitch in the die package. This paper proposes solution derived (sol-gel based) nano-grained copper and lead free solders for fine-pitch high strength nano-structured interconnects. In this process, metal-based organic polymer solutions are heat-treated in reducing atmosphere to form metallic copper and lead-free solders (Sn-Ag-Cu). The key is to achieve ultra homogeneous mixing at atomic to molecular level. The precursors were mixed in solvent and refluxed under inert atmosphere at 125/spl deg/C to form metallic Cu/Sn-Ag-Cu complex solutions. The homogenous gel obtained from the hydrolysis of sol-gel precursor solution is heat treated under inert atmosphere at temperatures below 350/spl deg/C to achieve the desired compositions. Among a large number of methods for metal deposition, sol-gel technology, based on thermal decomposition of metal-organic compounds, can prove to be the most convenient and inexpensive for industrial applications.

Evaluation of low stress dielectrics for board application

Abstract: The objective of this research is to evaluate and qualify low stress dielectric materials for multi-layer sequential buildup process. It is expected that a low CTE dielectric, such as Liquid Crystal Polymer (LCP), or a low modulus dielectric, such as ABSORE30NDTM will reduce the dielectric film stress generated due to CTE mismatch between the substrate and the dielectric layer. These dielectrics were laminated onto 3 board samples: carbon cyanate ester, carbon epoxy, and double-treated FR4. Atomic Force Microscope (AFM) was used to determine the surface roughness of various boards. Peel strength measurement was performed to quantify the adhesion between the dielectric and the board. Test beds were assembled using PB8 flip chips for thermo-mechanical reliability assessment.