Ricardo Carmona-Galan

TL;DR: The ACE16k as mentioned in this paper is a member of the third generation of the ACE chips, which is designed in a 0.35-/spl mu/m standard CMOS technology, and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm/sup 2/ and 82.5 GOPS /W.

TL;DR: A new methodology and experimental implementations for real-time wave-based robot navigation in a complex, dynamically changing environment is introduced and principles of computation in reaction-diffusion (RD) nonlinear active media where autowaves are used for information processing purposes can be considered as RD computing devices.

TL;DR: A 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO process and fully functional, which implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power.

TL;DR: The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers, and the Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.

TL;DR: The last test carried out, involving the prescribed burning of a 95 × 20-m shrub plot, confirmed the high degree of reliability of the approach in terms of both successful early detection and a very low false-alarm rate.