R
Rimas Avizienis
Researcher at University of California, Berkeley
Publications - 20
Citations - 2654
Rimas Avizienis is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Switched capacitor & System on a chip. The author has an hindex of 14, co-authored 20 publications receiving 2165 citations.
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Journal ArticleDOI
Single-chip microprocessor that communicates directly using light
Chen Sun,Chen Sun,Mark T. Wade,Yunsup Lee,Jason S. Orcutt,Jason S. Orcutt,Luca Alloatti,Michael Georgas,Andrew Waterman,Jeffrey M. Shainline,Jeffrey M. Shainline,Rimas Avizienis,Sen Lin,Benjamin Moss,Rajesh Kumar,Fabio Pavanello,Amir H. Atabaki,Henry Cook,Albert Ou,Jonathan Leu,Yu-Hsin Chen,Krste Asanovic,Rajeev J. Ram,Milos A. Popovic,Vladimir Stojanovic +24 more
TL;DR: This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Proceedings ArticleDOI
Chisel: constructing hardware in a Scala embedded language
Jonathan Bachrach,Huy Vo,Brian Richards,Yunsup Lee,Andrew Waterman,Rimas Avizienis,John Wawrzynek,Krste Asanovic +7 more
TL;DR: Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages, is introduced by embedding Chisel in the Scala programming language, raising the level of hardware design abstraction.
Proceedings ArticleDOI
RAMP gold: an FPGA-based architecture simulator for multiprocessors
Zhangxi Tan,Andrew Waterman,Rimas Avizienis,Yunsup Lee,Henry Cook,David A. Patterson,Krste Asanovica +6 more
TL;DR: The RAMP Gold prototype is a high-throughput, cycle-accurate full-system simulator that runs on a single Xilinx Virtex-5 FPGA board, and which simulates a 64-core shared-memory target machine capable of booting real operating systems.
The RISC-V Instruction Set Manual Volume 2: Privileged Architecture Version 1.7
TL;DR: This document describes the RISC-V privileged architecture, which covers all aspects of Risc-V systems beyond the user-level ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices.
Proceedings ArticleDOI
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators
Yunsup Lee,Andrew Waterman,Rimas Avizienis,Henry Cook,Chen Sun,Vladimir Stojanovic,Krste Asanovic +6 more
TL;DR: This is the first dual-core processor to implement the open-source RISC-V ISA designed at the University of California, Berkeley and integrates a custom vector accelerator alongside each single-issue in-order scalar core.