Jonathan Leu

TL;DR: This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

TL;DR: This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process and demonstrates an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits.

TL;DR: A set of link component models for performing interconnect design-space exploration connected to the underlying device and circuit technology is presented, demonstrating the link-level interactions between components in achieving the optimal degree of parallelism and energy-efficiency.

TL;DR: This work demonstrates a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process, and introduces deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss.

TL;DR: A Cadence toolkit library written in VerilogA for simulation of electro-optical systems is presented and it is shown that the results match other simulations and analytic solutions that have previously been compared to theory.