Nanocrystals (NCs), representing a zero-dimensional system, are an ideal platform for exploring quantum phenomena on the nanoscale, and are expected to play a major role in future electronic and photonic devices. Here we review recent progress in the growth, characterization and utilization of some group-IV semiconductors (Si and Ge), metal and high-k NCs for silicon planar technology compatible light-emitting and floating gate memory devices. We first introduce the size-dependent electrical and optical properties of Si and Ge NCs. We outline some of the schemes to achieve light emission from indirect band gap Si and Ge NCs embedded in different high band gap oxide matrices. In particular, special emphasis is given on the review of the advances in Ge NCs because of some of their intriguing electronic and optical properties. We then describe the use of semiconductor and metal NCs as floating gates for non-volatile memory devices to achieve high data retention and faster program/erase speeds. The exploitation of high-k oxides with tunable and variable injection barriers for improved charge storage devices is discussed. Finally, the integration of single and multilayer metallic NCs and multilayer high-k oxides as floating gates is explored by the fabrication and testing of memory transistors.

https://iopscience.iop.org/article/10.1088/0022-3727/46/15/153001/pdf

Nanocrystals for silicon-based light-emitting and memory devices

Surface tension-driven self-alignment is a passive and highly-accurate positioning mechanism that can significantly simplify and enhance the construction of advanced microsystems. After years of research, demonstrations and developments, the surface engineering and manufacturing technology enabling capillary self-alignment has achieved a degree of maturity conducive to a successful transfer to industrial practice. In view of this transition, a broad and accessible review of the physics, material science and applications of capillary self-alignment is presented. Statics and dynamics of the self-aligning action of deformed liquid bridges are explained through simple models and experiments, and all fundamental aspects of surface patterning and conditioning, of choice, deposition and confinement of liquids, and of component feeding and interconnection to substrates are illustrated through relevant applications in micro- and nanotechnology. A final outline addresses remaining challenges and additional extensions envisioned to further spread the use and fully exploit the potential of the technique.

https://pubs.rsc.org/en/content/articlepdf/2017/sm/c6sm02078j

Surface tension-driven self-alignment

Self-assembly of multichips with metal microbump electrodes is demonstrated by using water surface tension to increase the stacking throughput/yield and chip alignment accuracy of conventional chip-to-wafer 3-D integration. Three-dimensional microbump interconnects are formed by self-assembly with thermal compression at 200°C. Chips with In-Au microbumps with pitches of 10 and 20 μm are tightly bonded to Si wafers after the flip-chip self-assembly process, resulting in high alignment accuracies of 0.8 and 0.2 μm in the x - and y-directions, respectively. Selective hydrophilization by 172-nm excimer lamp irradiation gives a high wettability contrast between hydrophilic chip bonding areas and hydrophobic surrounding areas on the wafers. This assists high-precision multichip self-assembly. A 2500-In-Au-microbump daisy chain is formed with a yield of 100% by flip-chip self-assembly, and it exhibits ohmic contact. The resistance is sufficiently low for 3-D large-scale integration application, being comparable to that obtained by conventional mechanical chip alignment.

Multichip-to-Wafer Three-Dimensional Integration Technology Using Chip Self-Assembly With Excimer Lamp Irradiation

A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.

Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology

A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates ( 118, 128 ) on a first substrate area ( 111 ) which are encapsulated in one or more planar dielectric layers ( 130 ) prior to forming in-laid high-k metal select gates and CMOS transistor gates ( 136, 138 ) in first and second substrate areas ( 111, 113 ) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate

Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D) and hetero integration of complementary metal-oxide semiconductors (CMOS) and microelectromechanical systems (MEMS). By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF) aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

https://www.mdpi.com/2072-666X/2/1/49/pdf

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

We report high-performance MOSFET nonvolatile memory with high-density cobalt-nanodots (Co-NDs) floating gate (the density is as high as 4-5 × 1012 /cm 2 and the size is ~2 nm) and HfO2 high-k blocking dielectric. The device is fabricated using a gate-last process. A large memory window, high-speed program/erase (P/E), long retention time, and excellent endurance till 106 P/E cycles are obtained. In addition, the discrete Co-NDs make dual-bit operation successful. The high performance suggests that high work-function Co-NDs combined with high-k blocking dielectric have a potential as a next-generation nonvolatile-memory candidate.

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $\hbox{HfO}_{\bf 2}$ High-k Blocking Dielectric

In this letter, cobalt nanodots (Co-NDs) had been formed via a self-assembled nanodot deposition. High resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of ∼2 nm and high density of (4–5)×1012/cm2. The metal-oxide-semiconductor device with high density Co-NDs floating gate and high-k HfO2 blocking dielectric exhibits a wide range memory window (0–12 V) due to the charge trapping into and distrapping from Co-NDs. After 10 years retention, a large memory window of ∼1.3 V with a low charge loss of ∼47% was extrapolated. The relative longer data retention demonstrates the advantage of Co-NDs for nonvolatile memory application.

Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric

In this letter, the formation of high density tungsten nanodots (W-NDs) embedded in silicon nitride via a self-assembled nanodot deposition is demonstrated. In this method, tungsten and silicon nitride are cosputtered in high vacuum rf sputtering equipment. The W-NDs with small diameters (1–1.5 nm) and high density (∼1.3×1013/cm2) were achieved easily by controlling W composition; this is the ratio of total area of W chips to that of silicon nitride target. The metal-oxide-semiconductor memory device was fabricated with high density W-NDs floating gate and high-k HfO2 blocking dielectric. A wide range memory window (0–29 V) was obtained after bidirectional gate voltages sweeping with range of ±1–±23 V. It is feasible to design the memory window with propriety power consumption for nonvolatile memory application.

Toshiya Kojima

Papers

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $\hbox{HfO}_{\bf 2}$ High-k Blocking Dielectric

Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric

Formation of high density tungsten nanodots embedded in silicon nitride for nonvolatile memory application