Showing papers by "Robert Bogdan Staszewski published in 2007"

Linearization of a transmit amplifier

Abstract: A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.

All-Digital PLL With Ultra Fast Settling

Abstract: A fully digital frequency synthesizer for RF wireless applications has recently been proposed At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS

Software reconfigurable digital phase lock loop architecture

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

Predistortion calibration and built in self testing of a radio frequency power amplifier using subharmonic mixing

Abstract: A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog/RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.

RF Built-in Self Test of a Wireless Transmitter

Abstract: RF frequency synthesizers and transmitters for wireless system-on-chips have recently migrated to low-cost deep-submicrometer CMOS processes that facilitate all-digital implementations. In addition to all the benefits of lower power, lower silicon cost, reduced board area, and improved performance that the scaled CMOS integration entails, the testing costs for RF performance and wireless standard compliance could also be drastically reduced. In this brief, we propose a built-in self test (BIST) method, which is based on the premise that the internal frequency synthesizer and transmitter signals are in digital format allowing for digital signal processing to ascertain the RF performance without external test equipment. With the RF BIST capability, millions of SoCs can be calibrated and tested in a production environment using a low cost digital tester while benefiting from increased test coverage and reduced test time and cost. The presented techniques have been successfully implemented in two generations of commercial digital RF processors: 130-nm Bluetooth and 90-nm GSM single-chip radios

Adaptive spectral noise shaping to improve time to digital converter quantization resolution using dithering

Abstract: A novel and useful apparatus for and method of improving the quantization resolution of a time to digital converter in a digital PLL using noise shaping. The TDC quantization noise shaping scheme is effective to reduce the TDC quantization noise to acceptable levels especially in the case of integer-N channel operation. The mechanism monitors the output of the TDC circuit and adaptively generates a dither (i.e. delay) sequence based on the output. The dither sequence is applied to the frequency reference clock used in the TDC which adjusts the timing alignment between the edges of the frequency reference clock and the RF oscillator clock. The dynamic alignment changes effectively shape the quantization noise of the TDC. By shaping the quantization noise, a much finer in-band TDC resolution is achieved resulting in the quantization noise being pushed out to high frequencies where the PLL low pass characteristic effectively filters it out.

Computation parallelization in software reconfigurable all digital phase lock loop

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter

Abstract: A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.

Local oscillator incorporating phase command exception handling utilizing a quadrature switch

Abstract: A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited modulation range to handle the large modulation ranges demanded by modern wideband wireless standards such as 3G WCDMA, etc. A controllable oscillator generates an RF signal having four quadrature phases in accordance with an input command signal. An exception handler compares the frequency command information against a threshold. If it exceeds the threshold a phase jump and a residue frequency command are generated. The residue frequency command is input to an oscillator which is operative to generate an RF signal having four quadrature phases. The phase jump is input to a quadrature switch which functions to select one of the four quadrature phase signals as the output RF signal which is then fed to a digital power amplifier.

Local oscillator with non-harmonic ratio between oscillator and RF frequencies using pulse generation and selection

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N f RF . The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q) f RF , wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

Built-in Self Testing of a DRP-Based GSM Transmitter

Abstract: We present a novel approach for built-in self-testing (BIST) of an RF wireless transmitter. This approach, based on fully-digital hardware and on software algorithms, allows the testing of the transmitter's analog/RF circuitry while providing low-cost replacements for the costly traditional RF tests. The testing approach is structural in nature and substitutes for the commonly employed RF performance testing of high-cost test equipment and extended test times. The test coverage achieved for the analog circuitry is maximized to approach 100% and the test-time and associated test costs are minimized. The presented techniques have been successfully verified in a commercial 90 nm CMOS single-chip GSM radio based on the Digital RF Processor (DRPtrade) technology.

Delay alignment in a closed loop two-point modulation all digital phase locked loop

Abstract: A novel apparatus for and method of delay alignment in a closed loop two-point modulation all digital phase locked loop (ADPLL). The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provided using multiple clock domains, tapped delay lines and clock adjustment circuits.

Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation with jitter estimation and correction

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.

Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS

Abstract: We present a fully integrated analog path for a 3 G polar transmitter in 90 nm CMOS. It includes a quad band Digitally Controlled Oscillator providing modulation for the phase data and a single stage Digital Pre-Power Amplifier that combines the phase and amplitude signals while providing the dynamic range for WCDMA. The chip, with integrated LDOs, consumes 60 mA from a 1.4 V supply while providing 11 dBm CW power at 1950 MHz, 87 dB dynamic range without any calibration, and PN of -157 dBc/Hz at 40 MHz.

Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. A synthesizer provides 4/3 the desired frequency fRF. This frequency is divided by two to obtain in-phase and quadrature square waves at ⅔ fRF. The in-phase signal is divided by two again to obtain in-phase and quadrature square waves at ⅓ fRF. The signals are then logically combined using XOR operations to obtain I and Q branch signals containing spectral spurs. Since the spurs are located in non-disturbing bands, they can be filtered out resulting in the desired output signal.

Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, soc including such converter and method of phase detection for use in synthesizing a clock signal

Abstract: A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.

Computation spreading for spur reduction in a digital phase lock loop

Abstract: A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.

Verification of Digital RF Processors: RF, Analog, Baseband, and Software

Abstract: Single-chip RF SoCs are seeing widespread acceptance in wireless applications. In this paper we address the issue of design verification of single-chip RF SOCs in a framework that accepts RF input and analyzes receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. No comprehensive methodology exists to date for designing such complex systems. This paper present a novel approach that allows building complex RF SoC systems based on VHDL modeling and simulation and opens up major avenues of model development for RF and analog circuits. This approach has been successfully applied to verify two generations of digital RF processors (DRP) in deep-submicron technologies

On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios

Abstract: A new all-digital phase-locked loop (ADPLL) for wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all- digital tuning of a digitally-controlled oscillator (DCO). Due to its digital intensive structure, the ADPLL is well suited for single-chip radio solutions fabricated using state-of-the- art low cost and power nanometer-scale CMOS processes. Being integrated with a digital signal processor (DSP), the ADPLL parameters can be properly controlled and seamlessly reconfigured using the available on-chip DSP unit making the ADPLL a software defined radio (SDR) platform. In this paper, we present a DSP based technique for the fully dynamic control of the ADPLL settling performance that allows the loop band width to be seamlessly widened or narrowed allowing for fast frequency acquisition or tracking with excellent phase noise and spurious performance, respectively. The arbitrary and dynamic control of the frequency synthesizer loop bandwidth will address the dynamically varying nature of a multi-radio multi- standard SDR environment.

Minimization of rms phase error in a phase locked loop by dithering of a frequency reference

Abstract: A novel and useful apparatus for and method of minimizing the phase distortions experienced at the output of a phase locked loop (PLL) by dithering of its input frequency reference to overcome additive interference that is parasitically suffered on it. The frequency reference signal is dithered in a controlled manner using either indirect or direct coupling. The dither signal may be a single clock or is generated by switching between two or more of the existing clock signals generated, or may be produced by a dedicated pseudo-random noise generator having specific spectral properties. In indirect coupling, the dither signal is coupled through a bond wire sufficiently close in proximity to the frequency reference circuit input. This dominates the jitter inflicted onto the frequency reference signal and upconverts its spectral content to higher frequency, thus eliminating the more damaging low-frequency jitter caused by the interfering RF signal. In direct coupling, the dither signal is coupled to the reference frequency input using a network of components directly connected thereto.

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications

Abstract: A new all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all-digital tuning of a digitally-controlled oscillator (DCO). In this paper, we present novel time-domain modeling and simulation techniques of the ADPLL phase detection mechanism as well as the frequency perturbation and phase noise characteristics of the DCO. The modeling principles are demonstrated for a GSM standard and validated through experimental results.

Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

Abstract: The paper proposed estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which exhibit a certain level of random and systematic mismatch. The techniques presented are employed in a commercial single-chip GSM/EDGE radio realized in 90 nm CMOS

Parallel redundant single-electron device and method of manufacture

Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

A Practical Step Forward Toward Software-Defined Radio Transmitters

Abstract: After many years of research and development in the wireless communication community, software defined radio (SDR) is no longer an unachievable dream In this paper, we present a significant step forward toward practical SDR transmitters Motivated by the reconfigurability, programmability and available computational power in a commercial Digital RF Processor (DRPTM)-based single-chip GSM/EDGE radio, we succeeded to modulate the RF carrier with P25 compliant C4FM (continuous 4-level FM) data P25 is a digital public safety standard that operates in the 746-806 MHz frequency band, which is different from the normal operation band of the GSM/EDGE chip The modulation is based completely on software without need for any hardware modifications The measurement results show that the transmitted signal spectrum is compliant with the P25 standard specifications We also show that the work presented in this paper can be extended to provide more elaborate modulation schemes

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS

Abstract: The relentlessly increasing bandwidths and decreasing costs of high-volume communication systems such as cellular handsets have been enabled by sophisticated digital signal processing techniques made practical by the continued scaling of CMOS technology. However, high-performance analog, mixedsignal, and RF circuitry is also required in these systems, and intense market pressure usually dictates that as much of it as possible be integrated along with the digital circuitry in the same technology. Unfortunately, the design of such circuitry becomes increasingly challenging as CMOS technology is scaled into the nanometer regime (<100 nm); low supply voltages, high 1/f noise, high device non-linearity, poor signal isolation, and device leakage limit the effectiveness of traditional analog circuit topologies in critical communication system blocks such as amplifiers, mixers, data converters, and phase-locked loops. This short course will explain the fundamental limitations faced by those designing such blocks in nanometer CMOS, and present state-of-the-art circuit and system-level techniques for addressing these limitations. It is intended for both entry-level and experienced engineers.

Software Aspects of the Digital RF Processor (DRP TM )

Abstract: This paper presents an overview of software aspects of the first-ever single-chip GSM radio realized in 90 nm CMOS. It demonstrates benefits of using highly programmable digital control logic in a wireless SoC system. It also describes a micro-processor design in the digital RF processor (DRP) and how it controls compensation for process, voltage, temperature (PVT) variations of the analog and RF circuits to meet the required RF performance.

Single-Electron Injection/Extraction Device for a Resonant Tank Circuit and Method of Operation Thereof

Abstract: A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the oscillator circuit tank circuit. The system further includes a synchronizer coupled to the single-electron device and configured to cause the single-electron device to inject the single electron into the resonant tank circuit at a phase based on an extreme (maximum or minimum) electrical characteristic output of the resonant tank circuit.

Single-Electron Tunnel Junction for a Complementary Metal-Oxide Device and Method of Manufacturing the Same

Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

Calibration circuitry and delay cells in rectilinear RF power amplifier

Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.