The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

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Design of Analog CMOS Integrated Circuits

The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

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Analysis and Design of Analog Integrated Circuits

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.

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A general theory of phase noise in electrical oscillators

We describe a distributed position-based network protocol optimized for minimum energy consumption in mobile wireless networks that support peer-to-peer communications. Given any number of randomly deployed nodes over an area, we illustrate that a simple local optimization scheme executed at each node guarantees strong connectivity of the entire network and attains the global minimum energy solution for stationary networks. Due to its localized nature, this protocol proves to be self-reconfiguring and stays close to the minimum energy solution when applied to mobile networks. Simulation results are used to verify the performance of the protocol.

Minimum energy mobile wireless networks

Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, low-order, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory.

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Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs

Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular performance aspects are summarized, and examples are given.

MOS operational amplifier design-a tutorial overview

Passive inductors and LC filters fabricated in standard Si IC technology are demonstrated. Q-factors from three to eight and inductors up to 10 nH in the gigahertz range have been realized. Measurements on a five-pole maximally flat low-pass filter give midband insertion loss and -3 dB bandwidth close to the nominal design values of 2.25 dB and 880 MHz. >

Si IC-compatible inductors and LC passive filters

A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.

Robert G. Meyer

Papers

Analysis and Design of Analog Integrated Circuits

Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs

MOS operational amplifier design-a tutorial overview

Si IC-compatible inductors and LC passive filters

A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration