R
Rosilde Corvino
Researcher at Eindhoven University of Technology
Publications - 21
Citations - 187
Rosilde Corvino is an academic researcher from Eindhoven University of Technology. The author has contributed to research in topics: Very long instruction word & Design space exploration. The author has an hindex of 9, co-authored 21 publications receiving 180 citations. Previous affiliations of Rosilde Corvino include Centre national de la recherche scientifique & Intel.
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Journal ArticleDOI
ASAM: Automatic architecture synthesis and application mapping
Lech Jozwiak,Menno Lindwer,Rosilde Corvino,Paolo Meloni,Laura Micconi,Jan Madsen,Erkan Diken,Deepak Gangadharan,Roel Jordans,Sebastiano Pomata,Paul Pop,Giuseppe Tuveri,Luigi Raffo,Giuseppe Notarangelo +13 more
TL;DR: An overview of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program is presented, which system, design, and electronic design automation (EDA) concepts seem to be adequate to address the challenges and solve the problems.
Proceedings ArticleDOI
ASAM: Automatic Architecture Synthesis and Application Mapping
Lech Jozwiak,Menno Lindwer,Rosilde Corvino,Paolo Meloni,Laura Micconi,Jan Madsen,Erkan Diken,Deepak Gangadharan,Roel Jordans,Sebastiano Pomata,Paul Pop,Giuseppe Tuveri,Luigi Raffo +12 more
TL;DR: An over-view of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program is presented and which system, design, and electronic design automation concepts seem to be adequate to resolve the problems and address the challenges.
Proceedings ArticleDOI
Exploring processor parallelism: Estimation methods and optimization strategies
TL;DR: In this article, the issue-width of an application specific VLIW issue is automatically selected based on a force-based parallelism measure, which is capable of estimating the required issuewidth within 3% on average.
Proceedings ArticleDOI
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops
TL;DR: This paper proposes a method for a concurrent exploration of data and task parallelism when using loop transformations to optimize data transfer and storage mechanisms for both single and multiple communicating nested loops.
Journal ArticleDOI
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths
TL;DR: The use of heterogeneous vector widths and a method to explore the heterogeneousvector widths for VLIW ASIPs are proposed and the associated design automation tools are explained.