Showing papers by "Rourab Paul published in 2016"

Common Readout Unit (CRU) - A new readout architecture for the ALICE experiment

Abstract: The ALICE experiment at the CERN Large Hadron Collider (LHC) is presently going for a major upgrade in order to fully exploit the scientific potential of the upcoming high luminosity run, scheduled to start in the year 2021. The high interaction rate and the large event size will result in an experimental data flow of about 1 TB/s from the detectors, which need to be processed before sending to the online computing system and data storage. This processing is done in a dedicated Common Readout Unit (CRU), proposed for data aggregation, trigger and timing distribution and control moderation. It act as common interface between sub-detector electronic systems, computing system and trigger processors. The interface links include GBT, TTC-PON and PCIe. GBT (Gigabit transceiver) is used for detector data payload transmission and fixed latency path for trigger distribution between CRU and detector readout electronics. TTC-PON (Timing, Trigger and Control via Passive Optical Network) is employed for time multiplex trigger distribution between CRU and Central Trigger Processor (CTP). PCIe (Peripheral Component Interconnect Express) is the high-speed serial computer expansion bus standard for bulk data transport between CRU boards and processors. In this article, we give an overview of CRU architecture in ALICE, discuss the different interfaces, along with the firmware design and implementation of CRU on the LHCb PCIe40 board.

NIST Statistical Test Suite

Abstract: The NIST Statistical Test Suite has 15 tests. The principal strategy of the NIST Statistical Test Suite is to judge statistical randomness property of random bit generating algorithms. Based on 300 to 500 different keys, the algorithm generates a series of even number of different long random sequences of n bits, n varying between 13 and 15 lacs, each of which is tested by the 15 tests. Each test has a specific statistic parameter for bit sequences under the assumption of randomness and calculates the deviation of the respective statistic parameter for the series of tested bit sequences.

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Abstract: Field programmable gate arrays (FPGAs) are readily affected by transient faults in the presence of radiation and other environmental hazards compared to application specific integrated circuits. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from soft errors arising from transient faults. In this letter, modified matrix code (MMC) is used for multibit error correction in FPGA-based systems, and dynamic partial reconfiguration is considered to reduce the reconfiguration time. We propose a first of its kind methodology for novel transient fault correction using MMC for FPGAs. To validate the design, the proposed method has been tested on a Kintex FPGA and its performance has been estimated in terms of hardware complexity, power consumption, overhead, and error correction efficiency.

Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment

Abstract: This paper presents a novel design for single channel error resilient secured multi-gigabit optical link for High-Energy Physics (HEP) experiment. The work discusses the logic core implemented on the latest Altera high performance Arria10 FPGA board, having 20nm chip technology. A novel data communication scheme is proposed for this HEP experiment that preserves the DC-balance of the line and allows forward error correction (FEC) with encryption. It is implemented through concatenated blocks of Scrambler, Golay triple error correction coder, AES (Advanced Encryption Standard) cipher and Helical Interleaver. The link operates at a frequency of 8.192 Gbps. Novelty of our design is justified through the performance measurement of the minipod-optical transmitters/receivers.

Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock.

Abstract: RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 bytes are processed in a FPGA embedded system using multiple coprocessors functioning in parallel. The PKRS process is tuned to form as many S-boxes as required by particular design architectures involving multiple coprocessors, each one undertaking byte-by-byte processing. Following a ecent idea [1] [2] the speed of execution of each processor is also enhanced by another fold if the byte-by-byte processing is replaced by a scheme of processing two consecutive bytes together. Adopting some new innovative concepts, three hardware design architectures are proposed in a suitable FPGA embedded system involving 1, 2 and 4 coprocessors functioning in parallel and a study is made on accelerating RC4 by processing bytes in byte-by-byte mode achieving throughputs from 1-byte-in-1-clock to 4-bytes-in-1-clock. The hardware designs are appropriately upgraded to accelerate RC4 further by processing 2 onsecutive RC4 bytes together and it has been possible to achieve a maximum throughput of 8-bytes per clock in Xilinx Virtex-5 LX110t FPGA [3] architecture followed by secured data communication between two FPGA boards.

Implementation of I2C bus master controller for CRU Slow Control in ALICE at LHC

Abstract: The ALICE (A Large Ion Collider Experiment) collaboration plans for a major upgrade of the detectors during Long Shutdown 2 (LS2), to commence from the year 2020, in order to enhance the scientific discovery potential in the Run3 of the Large Hadron Collider (LHC) [1]. After LS2 the luminosities and hence the interaction rates will be increased by six times in Run3. To cope up with the increased interaction rate and in turn the large event size, a new approach based on Common Readout Unit (CRU) is being developed. It is a functional block placed in between the detector systems, the Data Acquisition System (DAQ) and the central trigger processor. The communication between the Front-End Electronics (FEE) of the detectors and the DAQ via CRU is mainly composed of three functional subsystems, a fast trigger timing and distribution system to deliver the system clock and trigger information, a data acquisition link carrying the collected data from the detector to the control room and a slow control system carrying bidirectional traffic from the control room and the embedded electronics on the detector. The slow control system is responsible to distribute control sequences and collect status information from the embedded peripheral electronics in the detector. There is a welldefined protocol stack for the slow control communication through CRU to the detectors. Inter Integrated Circuit (I2C) bus protocol [2] is an integrated part of this hierarchy. This article presents the implementation of I2C master bus controller on Altera Field Programmable Gate Array (FPGA), which is an integral part of the slow control development for CRU project. Protocol stack for CRU slow control

Automatic flipping magnet type electromagnetic energy harvester

Abstract: A new flipping magnet type electromagnetic energy harvester (EEH) suitable for scavenging energy from low frequency vibrations is presented in this Letter. The proposed EEH has a spherical permanent magnet (SPM), which is free to move inside a spherical bobbin that carries coils. Two cylindrical permanent magnets are employed to flip the SPM fast, even if the frequency of vibration source is low. This induces sufficient voltage in the coil to convert to dc and use. No such scheme has been reported so far and the existing EEHs give very low induced voltage for low frequency vibrations <5 Hz. Two versions of the new EEH prototypes, were built and tested. The peak-to-peak open circuit voltage of version-1 was 3.5 V and the power density was 445 µW/cm3 for a matched load of 52.5 Ω at 3.5 Hz vibration. The power density of the version-2 harvester was 538.6 µW/cm3. One of the applications of the proposed EEH is to harvest energy from railway tracks, for powering trackside monitoring sensors. The prototype developed generated up to 2.44 mW for an emulated railway track vibration in the range of 4 Hz, which is a considerable improvement compared with the existing EEHs.