1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors. Owing to their excellent optoelectronic properties, Ge-on-Si photodetector can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and low-cost infrared imaging at low power consumption. This Review covers the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.

High-performance Ge-on-Si photodetectors

This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...

Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing

Silicon germanium (SiGe) has moved from being a research material to accounting for a small but significant percentage of manufactured semiconductor devices. This percentage is predicted to increase substantially as SiGe begins to be used in complementary metal oxide semiconductor (CMOS) technology in the future to substantially improve performance. It is the development of Si/SiGe heterostructures which has enabled band structure and strain engineering allowing Si/SiGe to be used in many different ways to improve conventional microelectronic device performance along with allowing new concepts to be explored. This paper presents a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system. In particular, the important device technologies in mainstream microelectronics of the SiGe heterostructure bipolar transistor (HBT) and strained-Si CMOS will be reviewed before future device and optoelectronics concepts are explored.

https://iopscience.iop.org/article/10.1088/0268-1242/19/10/R02/pdf

Si/SiGe heterostructures: from material and physics to devices and circuits

The integration of Ge photodetectors on silicon substrates is advantageous for various Si-based optoelectronics applications. We have fabricated integrated Ge photodiodes on a graded optimized relaxed SiGe buffer on Si. The dark current in the Ge mesa diodes, Js=0.15 mA/cm2, is close to the theoretical reverse saturation current and is a record low for Ge diodes integrated on Si substrates. Capacitance measurements indicate that the detectors are capable of operating at high frequencies (2.35 GHz). The photodiodes exhibit an external quantum efficiency of η=12.6% at λ=1.3 μm laser excitation in the photodiodes. The improvement in Ge materials quality and photodiode performance is derived from an optimized relaxed buffer process that includes a chemical mechanical polishing step within the dislocated epitaxial structure.

High-quality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers

Relaxed SiGe thin films are used as templates to control the nucleation of three-dimensional Ge islands on Si(100) substrates. Using the relaxed template, Ge islands form a rectangular array with all islands located exclusively above the intersections of dislocations. The registration is lost when the Ge growth temperature is lowered to 300 °C, and the Ge coverage is decreased to 0.4 nm.

Relaxed template for fabricating regularly distributed quantum dot arrays

Recent advances in the understanding and control of threading dislocations in substantially relaxed SiGe buffer layers on Si are presented. A model for threading dislocation flow in relaxed graded SiGe buffers is used to determine the potential lower limit of threading dislocation density in relaxed SiGe buffers. Greater densities than expected from the model are seen in relaxed graded alloys with final concentrations greater than 50%. We show that the culprits of the higher threading dislocation density are threading dislocation pile-ups. Observation of early development of pile-ups confirms that inhomogeneous misfit dislocation densities in the graded buffer form regions of more severe crosshatch on the surface that impede dislocation flow. By using chemomechanical planarization (CMP), deleterious pile-up formation can be avoided, and previously formed pile-ups can be destroyed by regrowth of a graded layer. Experiments with CMP and regrowth of graded layers suggest that dislocation annihilation can be effective at reducing threading dislocation densities to densities of the order expected by the model. High quality Ge on Si layers created with the CMP process were used as templates to grow high quality GaAs on Si with strong room temperature photoluminescence and record minority carrier lifetime.

Dislocations in Relaxed SiGe/Si Heterostructures

A method of processing semiconductor materials, including providing a monocrystalline silicon substrate (12) having a (001) crystallographic surface orientation; off-cutting the substrate to an orientation from about 2° to about 6° offset towards the (110) direction; and epitaxially growing a relaxed graded layer of a crystalline GeSi (14) on the substrate (12) and the structure obtained by the method.

S. B. Samavedam

Papers

Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing

High-quality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers

Relaxed template for fabricating regularly distributed quantum dot arrays

Dislocations in Relaxed SiGe/Si Heterostructures

Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon