S
S. Crowder
Researcher at IBM
Publications - 27
Citations - 774
S. Crowder is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Silicon on insulator. The author has an hindex of 17, co-authored 27 publications receiving 770 citations.
Papers
More filters
Patent
Semiconductor chip having both compact memory and high performance logic
Paul D. Agnello,Bomy A. Chen,S. Crowder,Ramachandra Divakaruni,Subramanian S. Iyer,Dennis Sinitsky +5 more
TL;DR: In this article, the authors proposed a process for fabrication of both compact memory and high performance logic on the same semiconductor chip, which consists of forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory and the logic regions, removing the protection layer over the logic region to expose the substrate, and forming the logic device in a logic region.
Journal ArticleDOI
Software defined environments: an introduction
Chung-Sheng Li,B. L. Brech,S. Crowder,D. M. Dias,Hubertus Franke,Matt R. Hogstrom,D. Lindquist,Giovanni Pacifici,Stefan Pappe,B. Rajaraman,Josyula R. Rao,Radha P. Ratnaparkhi,Rodney A. Smith,M. D. Williams +13 more
TL;DR: The key elements within software defined environments include capability-based resource abstraction, goal-based and policy-based workload definition, and outcome-based continuous mapping of the workload to the available resources.
Patent
Method for self-aligned vertical double-gate MOSFET
TL;DR: In this article, a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible.
Proceedings ArticleDOI
High-performance sub-0.08 /spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delay
Michael J. Hargrove,S. Crowder,Edward J. Nowak,R. Logan,L.K. Han,H. Ng,Asit Kumar Ray,D. Sinitsky,Peter Smeys,Fernando Guarin,J. Oberschmidt,Emmanuel F. Crabbe,D. Yee,L. Su +13 more
TL;DR: In this paper, the authors reported a high performance CMOS operating at 15 V with 119 ps nominal inverter delay at 006/008/spl mu/m L/sub eff/ for NMOS and PMOS.
Patent
Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor
William F Landers,Thomas M. Shaw,Diana Llera-Hurlburt,S. Crowder,Vincent J. McGahay,Sandra G. Malhotra,Charles R. Davis,Ronald D Goldblatt,Brett H. Engel +8 more
TL;DR: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions.