The Internet has led to the creation of a digital society, where (almost) everything is connected and is accessible from anywhere. However, despite their widespread adoption, traditional IP networks are complex and very hard to manage. It is both difficult to configure the network according to predefined policies, and to reconfigure it to respond to faults, load, and changes. To make matters even more difficult, current networks are also vertically integrated: the control and data planes are bundled together. Software-defined networking (SDN) is an emerging paradigm that promises to change this state of affairs, by breaking vertical integration, separating the network's control logic from the underlying routers and switches, promoting (logical) centralization of network control, and introducing the ability to program the network. The separation of concerns, introduced between the definition of network policies, their implementation in switching hardware, and the forwarding of traffic, is key to the desired flexibility: by breaking the network control problem into tractable pieces, SDN makes it easier to create and introduce new abstractions in networking, simplifying network management and facilitating network evolution. In this paper, we present a comprehensive survey on SDN. We start by introducing the motivation for SDN, explain its main concepts and how it differs from traditional networking, its roots, and the standardization activities regarding this novel paradigm. Next, we present the key building blocks of an SDN infrastructure using a bottom-up, layered approach. We provide an in-depth analysis of the hardware infrastructure, southbound and northbound application programming interfaces (APIs), network virtualization layers, network operating systems (SDN controllers), network programming languages, and network applications. We also look at cross-layer problems such as debugging and troubleshooting. In an effort to anticipate the future evolution of this new paradigm, we discuss the main ongoing research efforts and challenges of SDN. In particular, we address the design of switches and control platforms—with a focus on aspects such as resiliency, scalability, performance, security, and dependability—as well as new opportunities for carrier transport networks and cloud providers. Last but not least, we analyze the position of SDN as a key enabler of a software-defined environment.

https://publications.uni.lu/bitstream/10993/20596/1/survey_on_SDN.pdf

Software-Defined Networking: A Comprehensive Survey

Software-Defined Networking (SDN) is an emerging paradigm that promises to change this state of affairs, by breaking vertical integration, separating the network's control logic from the underlying routers and switches, promoting (logical) centralization of network control, and introducing the ability to program the network. The separation of concerns introduced between the definition of network policies, their implementation in switching hardware, and the forwarding of traffic, is key to the desired flexibility: by breaking the network control problem into tractable pieces, SDN makes it easier to create and introduce new abstractions in networking, simplifying network management and facilitating network evolution. In this paper we present a comprehensive survey on SDN. We start by introducing the motivation for SDN, explain its main concepts and how it differs from traditional networking, its roots, and the standardization activities regarding this novel paradigm. Next, we present the key building blocks of an SDN infrastructure using a bottom-up, layered approach. We provide an in-depth analysis of the hardware infrastructure, southbound and northbound APIs, network virtualization layers, network operating systems (SDN controllers), network programming languages, and network applications. We also look at cross-layer problems such as debugging and troubleshooting. In an effort to anticipate the future evolution of this new paradigm, we discuss the main ongoing research efforts and challenges of SDN. In particular, we address the design of switches and control platforms -- with a focus on aspects such as resiliency, scalability, performance, security and dependability -- as well as new opportunities for carrier transport networks and cloud providers. Last but not least, we analyze the position of SDN as a key enabler of a software-defined environment.

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

/pdf/device-scaling-limits-of-si-mosfets-and-their-application-299ftwsxth.pdf

Device scaling limits of Si MOSFETs and their application dependencies

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

In this work, we demonstrate the integration of trench DRAM into a 018 /spl mu/m copper BEOL technology which is fully compatible with our most advanced logic technology and requires no redesign of preexisting logic circuitry This technology offers a 0617 /spl mu/m/sup 2/ DRAM cell on the same chip as a 42 /spl mu/m/sup 2/ SRAM cell and dual damascene copper metallization with the highest reported device performance for a 15 V bulk silicon technology We demonstrate a fixable retention time of over 256 ms at 85/spl deg/C for the DRAM cell without any degradation in logic device performance or density

Integration of trench DRAM into a high-performance 0.18 /spl mu/m logic technology with copper BEOL

A semiconductor device having a silicon-on-insulator (SOI) structure includes a field-effect transistor having amorphized source and drain regions formed by implanting silicon or germanium ions into a silicon layer formed over a buried insulator. The fully amorphized source and drain regions ultimately result in permanent crystalline defects that cause p-n junction leakage which allows charge in the body of the device to dissipate, thereby improving the overall efficiency and performance of the device. The source and drain regions are amorphized throughout their entire thickness to prevent single crystal re-crystallization from occurring during annealing and other subsequent processing steps that can degrade the quality of the p-n leakage junctions.

Fully amorphized source/drain for leaky junctions

There is a method and system for capability-based resource allocation in a software-defined environment that performs the following steps (not necessarily in the following order): (i) determining a set of capability characteristics for a plurality of workload resources within a software-defined environment; (ii) determining a set of workload components for a specified workload; and (iii) identifying a set of workload resources from the plurality of workload resources to allocate to the specified workload based, at least in part, on the set of capability characteristics corresponding to each workload within the set of workload resources. A workload component of the set of workload components has a unique set of workload characteristics.

Capability-based abstraction of software-defined infrastructure

There is a method and system that includes establishing a security container that describes a workload and a set of resources that corresponds to the workload in a software-defined environment, determining a set of security criteria for the security container, monitoring the workload and the set of resources for security events based, at least in part, upon the set of security criteria, and responsive to identifying a security event, adjusting one or more security mechanisms. The steps of monitoring and adjusting are operated within the software-defined environment.

Security within a software-defined infrastructure

When DSB bonding interface falls into highly doped S/D direct silicon bonded (DSB) technology is shown to be scalable regions, there are concerns of high S/D leakage (due to the possible for 32 nm node and beyond for two integration schemes: solid phase defects in the DSB interface) and high S/D resistance due to epitaxy (SPE)-before-shallow trench isolation (STI) and STI-before-SPE. For SPE-before-STI, 32 nm node ground rules can be met by thinning DSB thickness to ~70 nm, which ensures complete removal of boundary defects by STI. For STI-before-SPE, a scaling-independent solution is provided by the use of 45deg rotated (100) base wafers which allow trench-defect-free SPE at the STI edges.

S. Crowder

Papers

Integration of trench DRAM into a high-performance 0.18 /spl mu/m logic technology with copper BEOL

Fully amorphized source/drain for leaky junctions

Capability-based abstraction of software-defined infrastructure

Security within a software-defined infrastructure

Scalability of Direct Silicon Bonded (DSB) Technology for 32nm Node and Beyond