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Patent

Method for self-aligned vertical double-gate MOSFET

TLDR
In this article, a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible.
Abstract
A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm −2 or greater; selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and saliciding any exposed silicon surfaces.

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Citations
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References
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Proceedings ArticleDOI

Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

TL;DR: In this article, a fabrication method that attains the "ideal" double-gate MOSFET device structure is reported, where the top and bottom gates are inherently self-aligned to the source/drain.
Proceedings ArticleDOI

Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy

TL;DR: In this paper, a super self-aligned double-gate MOSFET structure is proposed to implement ideal double-gated CMOS devices, where only one gate mask is used to define both top and bottom gates, so a perfectly aligned gate structure is obtained.
Journal ArticleDOI

Potential design and transport property of 0.1-/spl mu/m MOSFET with asymmetric channel profile

TL;DR: In this paper, the potential design and transport properties of a 0.1/spl mu/m n-MOSFET with asymmetric channel profile were investigated by Monte Carlo simulations.
Patent

Vertical double-gate field effect transistor

TL;DR: In this paper, a vertical double-gate field effect transistor (VDFET) was proposed, which includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate.
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