Exploring and identifying structure is even more important for multivariate data than univariate data, given the difficulties in graphically presenting multivariate data and the comparative lack of parametric models to represent it. Unfortunately, such exploration is also inherently more difficult.

Multivariate Density Estimation

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

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50 Years of CORDIC: Algorithms, Architectures, and Applications

From the Publisher: 
This is undoubtedly the most accessible book on digital signal processing (DSP) available to the beginner. Using intuitive explanations and well-chosen examples, this book gives you the tools to develop a fundamental understanding of DSP theory. The author covers the essential mathematics by explaining the meaning and significance of the key DSP equations. Comprehensive in scope, and gentle in approach, the book will help you achieve a thorough grasp of the basics and move gradually to more sophisticated DSP concepts and applications.

数字信号处理 = Understanding digital signal processing

Although arithmetic coding offers extremely high coding efficiency, it provides little or no security as traditionally implemented. We present a modified scheme that offers both encryption and compression. The system utilizes an arithmetic coder in which the overall length within the range [0,1) allocated to each symbol is preserved, but the traditional assumption that a single contiguous interval is used for each symbol is removed. Additionally, a series of permutations are applied at the input and the output of the encoder. The overall system provides simultaneous encryption and compression, with negligible coding efficiency penalty relative to a traditional arithmetic coder

Secure Arithmetic Coding

Many countries will experience the effects of an aging population, resulting in a high demand of healthcare facilities. Development of novel biomedical technologies is an urgent necessity to improve diagnostic services for this demographic. Electrocar diogram (ECG) and temperature recording have been used for more than 50 years in medical diagnosis to understand various biological activities [1], [2]. A more recent development, electronic pill technology, requires the integration of more complex systems on the same platform when compared to conventional implantable systems. A small miniaturized electronic pill can reach areas such as the small intestine and can deliver real time video images wirelessly to an external console. Figure 1 shows an electronic pill system (i.e., wireless endoscopy) for a medical monitoring system. The device travels through the digestive system to collect image data and transfers the data to a nearby computer for display with a distance of one meter or more. A high resolution videobased capsule endoscope produces a large amount of data, which can then be delivered over a high-capacity wireless link.

Easy-to-Swallow Wireless Telemetry

This paper describes the process of review, design, and delivery of a course in modern embedded systems, an international collaborative teaching project involving the University of New South Wales (Australia), Manchester University, and Imperial College, London University (United Kingdom). This project, being the first of its kind anywhere in the world, provides a learning environment that replicates the current industrial practice in embedded systems design in an easy and comprehensible setting, an environment where the processor, dedicated coprocessors, and software are all integrated to create a functional system such as used in sophisticated electronic devices, including mobile phones, Web phones, televisions, digital cameras, and personal digital assistants. Such collaborations are important in both reducing development costs in developing up-to-date, and increasingly sophisticated, courses and in addressing pedagogical issues that are common between computer and electrical engineering programs in all academic institutions. To assist students' learning experience, the course is supported with purpose built state-of-the-art programmable hardware and software development platforms, carefully planned laboratory experiments, lecture notes, weekly online quizzes, tutorials, and a companion CD-ROM as a learning tool. Since the introduction of this complete package, students' satisfaction, assessment results, and skills obtained through evaluation and assessment methods have improved markedly

Modernization of teaching in embedded systems design-an international collaborative project

The median filter is an effective device for the removal of impulse-based noise on video signals. This is due to the partial averaging effect of the median filter and its biasing of the input stream, rather than straight mathematical averaging. In this paper, we describe three realizations of median filter, built into as few as one field programmable logic device, which is capable of processing an incoming video data stream at a maximum (programmable logic device partially dependent) of around 30 MS/s. In total, four designs are considered, with a primary design, two variations on the primary design and an asynchronous version based on the primary design. Simulation of the primary design (both synchronous and asynchronous) has demonstrated its potential for reducing the area requirements of a median filter whilst not sacrificing either speed or accuracy.

FPGA implementation of a median filter

This brief presents a new CMOS logic family using the feedthrough evaluation concept and analyzes its sensitivity against technology parameters for practical applications. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (35.6%), and similar combined delay, power consumption and active area product (0.7% worst), while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS

JPEG2000 is a recently standardized image compression algorithm. The heart of this algorithm is the coding scheme known as embedded block coding with optimal truncation (EBCOT). This contributes the majority of processing time to the compression algorithm. The EBCOT scheme consists of a bit-plane coder coupled to a MQ arithmetic coder. Recent bit-plane coder architectures are capable of producing symbols at a higher rate than the existing MQ arithmetic coders can absorb. Thus, there is a requirement for a high throughput MQ arithmetic coder. We examine the existing MQ arithmetic coder architectures and develop novel techniques capable of absorbing the high symbol rate from high performance bit-plane coders, as well as providing flexible design choices

Concurrency techniques for arithmetic coding in JPEG2000

Increasing the throughput of the JPEG2000 block coder requires bit-plane and arithmetic coders capable of concurrent symbol processing. Previously described pipelined MQ coders are capable of consuming 1 symbol or less per clock cycle. We develop a new pipelined MQ coder that can process exactly two symbols per clock cycle. The technique is implemented on a FPGA, and is compared with our "Hypothesis Testing" arithmetic coder and a reference one symbol per cycle coder. Our implementation gives an increase in throughput of 1.9 times, at the cost of 1.7 times as much hardware, when compared to the reference coder. It also has 1.2 times the throughput, while consuming only 70% of the hardware associated with the Hypothesis Testing coder.

Saeid Nooshabadi

Papers

Modernization of teaching in embedded systems design-an international collaborative project

FPGA implementation of a median filter

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS

Concurrency techniques for arithmetic coding in JPEG2000

Improved throughput arithmetic coder for JPEG2000