S
Saibal Mukhopadhyay
Researcher at Georgia Institute of Technology
Publications - 432
Citations - 10232
Saibal Mukhopadhyay is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Computer science & CMOS. The author has an hindex of 40, co-authored 381 publications receiving 8814 citations. Previous affiliations of Saibal Mukhopadhyay include IBM & Purdue University.
Papers
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Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
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Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
TL;DR: A methodology to statistically design the SRAM cell and the memory organization using the failure-probability and the yield-prediction models and can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.
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Neurocube: a programmable digital neuromorphic architecture with high-density 3D memory
TL;DR: The basic architecture of the Neurocube is presented and an analysis of the logic tier synthesized in 28nm and 15nm process technologies are presented and the performance is evaluated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.
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A circuit-compatible model of ballistic carbon nanotube field-effect transistors
TL;DR: A novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit is presented, for the first time, both the I-V and the C-V characteristics of the device have been efficiently modeled for circuit simulations.
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Gate leakage reduction for scaled devices using transistor stacking
TL;DR: A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit.