There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The organization of behavior: A neuropsychological theory

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU)---deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs (caches, out-of-order execution, multithreading, multiprocessing, prefetching, ...) that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X - 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X - 80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

In-Datacenter Performance Analysis of a Tensor Processing Unit

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

/pdf/in-datacenter-performance-analysis-of-a-tensor-processing-4pmp83zqw4.pdf

Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems. This article aims to provide a comprehensive tutorial and survey about the recent advances toward the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic codesigns, being proposed in academia and industry. The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the tradeoffs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

Super-lattice thin-film thermoelectric coolers (TEC) are emerging as a promising technology for hot spot mitigation in microprocessors. This paper studies the prospect of on-demand cooling with advanced TECs integrated at the back of the heat spreader inside a package (integrated TEC). The thermal compact models of the chip and package with integrated TECs are developed and used for steady-state and transient temperature analysis. The control principles for TEC assisted transient cooling are presented and their impact on reducing thermal violations in microprocessors and TEC energy dissipations are discussed.

Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors

This paper shows that inductive integrated voltage regulators (IVR) provide significant immunity to traditional power attacks on crypto encryption engines based on time-domain analysis of the chip current. Frequency-domain analyses of envelope and duty cycle of the current are identified as new attack modes. The security-aware IVR design is discussed to provide additional immunity to power attack.

Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study.

Background The regulatory T cell (Treg) is essential for prevention of autoimmunity. In a preliminary study, we showed significant deficiency of Tregs (CD4CD25 T cells) in rheumatic heart disease (RHD) patients (an autoimmune disease), but the markers used could not reliably differentiate Treg from nonregulatory conventional T cells (Tcon). The study aim was to reassess the level of circulatory Tregs by using more specific markers. Methods 70 adults of RHD and 35 controls were studied. Patients were subdivided according to the extent of left-sided valvular involvement. 35 patients with significant mitral-valve disease only were enrolled in the univalvular group while 35 patents with significant involvement of both mitral and aortic-valves in the multivalvular group. Circulating Treg cell level was determined by flow-cytometry. Results Level of Tregs (CD4+CD25med–highCD127low Foxp3high) in CD4+ T lymphocyte was significantly lower in RHD patients compared to controls (median 0.6% versus 3.2%; p = 0.001) with no significant difference in Tcon cells (p = 0.94). Within the study group Treg count was significantly lower in patients with multivalvular-disease only (median 0.1% versus 3.2%; p = 0.001) with no significant difference in Treg cell count between the univalvular group and control (median 1.9% versus 3.2%, p = 0.10). Conclusion There is significant deficiency of circulating Tregs in patients of chronic RHD and the deficiency is greater in patients with multivalvular than univalvular involvement.

Circulating level of regulatory T cells in rheumatic heart disease: An observational study

“Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking. Time borrowing allows a pipeline to compensate the timing slack by borrowing time from the next pipeline stage and clock stretching pays back the borrowed time to the next pipeline stage. Thus, a system employing such dynamic timing control technique can prevent errors with a small performance penalty and eventually operate without safety margin. The net effect is better power-performance trade-off under voltage scaling i.e. lower power consumption for a target frequency or higher operating frequency for a target power. The proposed technique was validated using a prototype test-chip designed in 180-nm CMOS technology.

Timing error prevention using elastic clocking

A cardiac hydatid cyst is rare. We report a case of cardiac hydatid cyst localized in the atria which was diagnosed by two-dimensional echocardiography following a thromboembolic stroke. Surgical resection of the cyst was performed and histopathologic examination confirmed the diagnosis.

Saibal Mukhopadhyay

Papers

Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors

Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study.

Circulating level of regulatory T cells in rheumatic heart disease: An observational study

Timing error prevention using elastic clocking

Thromboembolism: A rare complication of cardiac hydatidosis