There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The organization of behavior: A neuropsychological theory

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU)---deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs (caches, out-of-order execution, multithreading, multiprocessing, prefetching, ...) that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X - 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X - 80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

In-Datacenter Performance Analysis of a Tensor Processing Unit

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

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Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems. This article aims to provide a comprehensive tutorial and survey about the recent advances toward the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic codesigns, being proposed in academia and industry. The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the tradeoffs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

3D integration provides opportunities to design high-bandwidth and low-power CMOS image sensors (CIS) [1–4]. The 3D stacking of pixel tier, peripheral tier, memory tier(s), and compute tier(s) enables high degree of parallel processing. Also, each tier can be designed in different technology nodes (heterogeneous integration) to further improve power-efficiency. This paper presents a case study of a smart 3D image sensor with integrated neuro-inspired computing for intelligent vision processing. Hardware acceleration of neuro-inspired computing has received much attention in recent years for recognition and classification [5]. We present the physical design of NeuroSensor, a 3D CIS with an integrated convolutional neural network (CNN) accelerator. The rationale for our approach is that 3D integration of sensor, memory, and computing will effectively harness the inherent parallelism in neural algorithms. We design the NeuroSensor considering different complexities of CNN platform, ranging from only feature extraction to complete classification, and study the trade-offs between complexity, performance, and power.

NeuroSensor: A 3D image sensor with integrated neural accelerator

In this paper, a proactive thermal management technique called “power multiplexing” is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called “proximity index” which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing.

/pdf/thermal-investigation-into-power-multiplexing-for-1ia19b14br.pdf

Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors

Round-the-clock surveillance requires robust object detection and tracking independent of lighting conditions. Fusing information from visual-infrared object detection network pair at feature level or decision level shows promising accuracy. However, such fused object detection network is not suitable for edge devices with limited processing power and memory. In this paper, we propose a technique to control spatial modality using feedback from the object detection network and create a mixed-modality image by eliminating the redundancy between visual and infrared information. Mixed-modality image enables object tracking with a single deep neural network as opposed to the decision- level fusion with two separate networks for visual image and infrared image. Proposed approach achieves at least 8% better object tracking accuracy than decision-level fusion while operating at 2X frame-rate and consuming 50% less energy.

Adaptive Control of Camera Modality with Deep Neural Network-Based Feedback for Efficient Object Tracking

High on-chip temperature can degrade chip performance, and increase high leakage power which contributes to a significant part of the total chip power consumption. Microfluidic cooling is believed to have better cooling ability than air cooling. However, very few experimental demonstrations of CMOS chips with integrated microfluidic cooling exist. This paper presents experimental results of a working CMOS chip capable of generating controllable heat and on-chip temperature sensing under air cooling and microfluidic cooling. Under natural air cooling, the leakage current increases exponentially by 1.9 X as the temperature increases from 26.3 °C to 57.6 °C. 18.8 °C temperature drop and 66.2% leakage current saving is achieved by microfluidic cooling compared to natural air cooling at heatflux 34.5 W/cm2. In addition, the time to reach a steady state in response to a sudden application of microfluidic cooling is only 48.5% of that of forced air cooling. Lastly, increasing the flow rate of microfluidic cooling does not decrease the temperature and leakage current much.

Enhancement in CMOS chip performance through microfluidic cooling

As the supply voltage (V DD ) approaches the device threshold voltage (V T ), the elevated temperature results in increased device current. This phenomenon is generally known as Inverse Temperature Dependence (ITD). In this paper, we propose a test structure with a built-in poly-resistor-based heater to characterize ITD in digital circuits. Our measurements from a 130nm test-chip show that the Zero-Temperature-Coefficient (ZTC) point varies by circuit type, and further fluctuates due to process variation. A more accurate ITD-sensitive thermal sensor is thus needed for better temperature tracking.

Saibal Mukhopadhyay

Papers

NeuroSensor: A 3D image sensor with integrated neural accelerator

Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors

Adaptive Control of Camera Modality with Deep Neural Network-Based Feedback for Efficient Object Tracking

Enhancement in CMOS chip performance through microfluidic cooling

Characterization of Inverse Temperature Dependence in logic circuits