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Saibal Mukhopadhyay

Researcher at Georgia Institute of Technology

Publications -  432
Citations -  10232

Saibal Mukhopadhyay is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Computer science & CMOS. The author has an hindex of 40, co-authored 381 publications receiving 8814 citations. Previous affiliations of Saibal Mukhopadhyay include IBM & Purdue University.

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Proceedings ArticleDOI

An on-chip autonomous thermoelectric energy management system for energy-efficient active cooling

TL;DR: An on-chip thermoelectric (TE) energy management system for energy-efficient on-demand active cooling of integrated circuits and provides cooling during critical thermal events by operating the TEM in the Peltier mode.
Proceedings ArticleDOI

Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration

TL;DR: In this article, the authors conduct a quantitative comparison between two 2.5D IC designs based on silicon vs. liquid crystal polymer (LCP) interposer technologies in the overall system level for the first time.
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Clinical Profiles, Outcomes, and Sex Differences of Patients With STEMI

TL;DR: NORIN-STEMI (North India ST-Segment Elevation Myocardial Infarction Registry) as discussed by the authors is an investigator-initiated prospective cohort study of patients presenting with STEMI at tertiary medical centers in North India.
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Management of diabetic dyslipidemia in Indians: Expert consensus statement from the Lipid Association of India.

TL;DR: In this article , the authors have developed a consensus statement to provide guidance for management of diabetic dyslipidemia in very high risk population, which is based on a series of 165 webinars conducted by the Lipid Association of India across the country from May 2020 to July 2021, involving 155 experts in endocrinology and cardiology and an additional 2880 physicians.
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Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures

TL;DR: A design approach based on microarchitecture adaptation to device-level temperature-dependent delay variations to realize average case performance that is superior to which can be achieved by using worst case design margins is advocated.