There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The organization of behavior: A neuropsychological theory

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU)---deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs (caches, out-of-order execution, multithreading, multiprocessing, prefetching, ...) that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X - 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X - 80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

In-Datacenter Performance Analysis of a Tensor Processing Unit

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

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Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems. This article aims to provide a comprehensive tutorial and survey about the recent advances toward the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic codesigns, being proposed in academia and industry. The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the tradeoffs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

3D integration enables the implementation of image sensors with integrated neural compute hardware capable of capturing images and performing neural classification in field. The inherent parallelism advantages of 3D stacking are ideal for high throughput imagers [1] [2] [3] as well neuromorphic hardware [4], [5] which are characterized by their large degree of parallel computation. This work presents a 3D stacked imaging system, composed of a digital pixel array, integrated with ReRAM based neural accelerator. A similar system, Neurosensor, was presented in [6], [7]. However, the imager in Neurosensor adopted a row by row pixel readout mechanism, and the neural accelerator was based on CMOS digital logic. In contrast, this system adopts digital pixels with in-pixel ADC which read out all pixels simultaneously for high throughput imaging, and integrates it with an ReRAM based processing-in-memory (PIM) analog neural accelerator. We present the system architecture and evaluate the various trade-offs in terms of hardware requirements, performance, and energy efficiency, as well as compare our system to Neurosensor.

3D Stacked High Throughput Pixel Parallel Image Sensor with Integrated ReRAM Based Neural Accelerator

This letter studies the interaction of the potential of through-oxide-via (TOV) and the electrical behavior of neighboring transistors in a 3-D stack of fully depleted silicon-on-insulator (FDSOI) devices. Using device simulation, we show that the back-gate electric field of FDSOI devices can be significantly modulated by the potential of TOVs placed in close proximity. Consequently, the change in the TOV potential results in appreciable variation in the threshold voltage and the leakage current of neighboring FDSOI devices.

Through-Oxide-Via-Induced Back-Gate Effect in 3-D Integrated FDSOI Devices

Carbon Nanotube Field-Effect Transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub 10 nm transistor era. This paper presents a novel method of circuit-compatible modeling of CNFETs in their ultimate performance limit. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE.

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Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation

This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write current. To satisfy the conflicting requirements of read margin and sensing accuracy, we propose a source-line biasing technique. Simulations in predictive 65-nm nodes show that the proposed solution simultaneously reduce the sensing errors and improve the read margin.

Saibal Mukhopadhyay

Papers

3D Stacked High Throughput Pixel Parallel Image Sensor with Integrated ReRAM Based Neural Accelerator

Through-Oxide-Via-Induced Back-Gate Effect in 3-D Integrated FDSOI Devices

Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation

Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices