There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The organization of behavior: A neuropsychological theory

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU)---deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs (caches, out-of-order execution, multithreading, multiprocessing, prefetching, ...) that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X - 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X - 80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

In-Datacenter Performance Analysis of a Tensor Processing Unit

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

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Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems. This article aims to provide a comprehensive tutorial and survey about the recent advances toward the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic codesigns, being proposed in academia and industry. The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the tradeoffs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

Introduction Atrial fibrillation and mitral stenosis, especially in combination, increase the risk of left atrial thrombus formation and systemic embolization. However, whether severe mitral regurgitation (MR) improves systemic hypercoagulable state in these patients is unclear. remains unclear. The study aims to study the impact of severe MR on systemic coagulation by the use of D-dimer levels. Methods It was a prospective, cross-sectional study done on 400 subjects consisting of 350 cases and 50 controls. The cases were divided into seven groups on basis of valvular pathology, rhythm, and presence of a clot. The D-dimer level was compared in all the subgroups. Result The mean age of the study population was 32.32±7.30 years with a 48% male population. The highest level of D-dimer was found in patients with thrombus (1.71 ± 1.74 µg/ml). Patients with mitral stenosis had significantly higher plasma D-dimer levels than the control group (p <0.001) while regardless of rhythm, patients with MR had a D-dimer level similar to the control group in sinus rhythm. Conclusion Severe MR reduces plasma D-dimer levels to control levels reflecting the protective effect against thrombus formation and systemic embolization.

Effect of Mitral Regurgitation on Systemic Coagulation Activity in Rheumatic Heart Disease as Assessed by D-dimer Levels.

A methodology is presented for on-line and realtime estimation of transient variations in temperature and average power of a chip after fabrication and packaging. Measurements from a 130nm CMOS test chip demonstrate the accuracy of the proposed approach.

On-line real-time temperature and power estimation of an IC using time-domain thermal filters

$A$ low-latency and high-throughput, configurable architecture for computing sparse Finite Impulse Response in real-time Radio Frequency domain is proposed. The massively parallel architecture uses distributed control in association with near-memory techniques to optimize area and power. It supports configurability in filter tap locations and handling of locally dense taps, making it more adaptable to Radio Frequency environments.

A Configurable Architecture for Efficient Sparse FIR Computation in Real-time Radio Frequency Systems

This paper presents a voltage regulator topology, implemented using low-voltage devices, for converting high input voltage (>4.5 V) to low output voltages with fine-grain control (0.3 to 1 V). The topology merges a Dickson's switched-capacitor stage with a current-mode inductive buck stage, and optimizes the frequency of operations to reduce the overall passive size. The proposed two-stage hybrid regulator, designed in 130-nm standard digital process, operates from 4.8 to 6 V at input and regulates output voltage as low as 0.3 V with a maximum output power of 90 mW and a peak efficiency of 69%.

A Scalable Hybrid Regulator For Down Conversion of High Input Voltage Using Low-Voltage Devices

This paper proposes a Fully Spiking Hybrid Neural Network (FSHNN) for energy-efficient and robust object detection in resource-constrained platforms. The network architecture is based on Convolutional SNN using leaky-integrate-fire neuron models. The model combines unsupervised Spike Time-Dependent Plasticity (STDP) learning with back-propagation (STBP) learning methods and also uses Monte Carlo Dropout to get an estimate of the uncertainty error. FSHNN provides better accuracy compared to DNN based object detectors while being 150X energy-efficient. It also outperforms these object detectors, when subjected to noisy input data and less labeled training data with a lower uncertainty error.

Saibal Mukhopadhyay

Papers

Effect of Mitral Regurgitation on Systemic Coagulation Activity in Rheumatic Heart Disease as Assessed by D-dimer Levels.

On-line real-time temperature and power estimation of an IC using time-domain thermal filters

A Configurable Architecture for Efficient Sparse FIR Computation in Real-time Radio Frequency Systems

A Scalable Hybrid Regulator For Down Conversion of High Input Voltage Using Low-Voltage Devices

A Fully Spiking Hybrid Neural Network for Energy-Efficient Object Detection