Physical limitations for CMOS technology have provided the way for manufacturing the quantum cellular automata technology-based hardware elements at Nano level. From the purpose of very high speed, area and low power consumption, this Nanotechnology has been taken into consideration. Improving their structures will lead promoting the system performance completely, because the Full adders are assumed as major and primary component of computational processors. In current study, the new layout of all single bit full adders in the quantum cellular automata's technology is introduced. In comparison with existing schemes, the suggested circuit has fewer cells and smaller area.

A new quantum-dot cellular automata full-adder

Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple- V t design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40 less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.

Design of energy-efficient and robust ternary circuits for nanotechnology

Designing efficient QCA logical circuits with power dissipation analysis

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

New robust QCA D flip flop and memory structures

Design and Evaluation of a Reconfigurable Fault Tolerant Quantum-Dot Cellular Automata Gate

Quantum-dot cellular automata (QCA), due to its unique characteristics like low power consumption, nanoscale design, and high computing speed is considered as an emerging technology, and it can be used as an alternative for CMOS technology in circuit design for quantum computers in the near future. XOR gate has many applications in the design of digital circuits in QCA. In this paper, an efficient novel structure of XOR gate is proposed in QCA. Also, a novel 1-bit comparator circuit, 1-bit full adder, binary to gray and gray to binary convertor code based on the proposed XOR is designed and simulated using QCADesigner 2.0.3. The simulation results demonstrated that the proposed structures provide improvements compared to previous works in terms of QCA cells count, area, and circuit cost.

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Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology

Nanomagnetic logic (NML) has recently been proposed as an attractive and promising implementation of QCA and also as a possible alternative to the CMOS technology. With this emerging technology, it is possible to process and store binary information according to the magnetization state of nanomagnets. Similar to other nanotechnologies, NML circuits are also sensitive to fabrication variations and thermal fluctuations. Therefore, it is highly consequential to improve the testability of these circuits. Circuits based on conservative logic inherently enhance test performance. In this paper, the Fredkin gate, which is one of the most famous conservative reversible gates has been designed and simulated in NML by considering the physical properties of nanomagnets. It can be used to design other testable and ultra-low-power NML circuits as well. OOMMF physical simulation tool is used to simulate and validate the proposed gate at room temperature. The results indicate the correct functionality of the design.

Design and evaluation of clocked nanomagnetic logic conservative Fredkin gate

Quantum-dot cellular automata (QCA) is a computational paradigm that is based on encoding information in terms of the configuration of charge among quantum dots without requiring current switches. Mostly, QCA cells have been realized by employing the electron switching in square quantum-dot cells. In this paper, a triangular metal-dot cell with a single electron is proposed to represent ternary information. Then, an inverter chain of the proposed triangle cells is suggested through juxtaposing the cells. Additionally, wire crossing and wire fan-out are the two inseparable subjects of QCA wire. A wire-crossing method is presented for the proposed ternary wire. Wire fan-out is also dealt with in this paper by an innovative approach. The correctness of operation of proposed cells and wires are thoroughly verified by applying the physical relations.

Triangular Quantum-Dot Cellular Automata Wire for Standard Ternary Logic

Quantum dots cellular automata is a new computing method in the nanotechnology that has considerable features such as low power, small dimension and high speed switch A QCA device stores logic based on the position of individual electrons The fundamental logic elements in QCA are the majority (Fig1 (a)) and inverter gates (Fig1 (b)) that operate based on the Coulomb repulsion between electrons [1]

Samira Sayedsalehi

Papers

Design and Evaluation of a Reconfigurable Fault Tolerant Quantum-Dot Cellular Automata Gate

Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology

Design and evaluation of clocked nanomagnetic logic conservative Fredkin gate

Triangular Quantum-Dot Cellular Automata Wire for Standard Ternary Logic

A combinational logic optimization for majority gate-based nanoelectronic circuits based on GA