S
Sandeep Kaur Kingra
Researcher at Indian Institute of Technology Delhi
Publications - 21
Citations - 1071
Sandeep Kaur Kingra is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: Computer science & Resistive random-access memory. The author has an hindex of 3, co-authored 13 publications receiving 584 citations. Previous affiliations of Sandeep Kaur Kingra include Chandigarh University & University Institute of Engineering and Technology, Panjab University.
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Journal ArticleDOI
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.
TL;DR: This paper proposes a novel ‘Simultaneous Logic in-Memory’ (SLIM) methodology which is complementary to existing LIM approaches in literature and demonstrates novel SLIM bitcells comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors.
Journal ArticleDOI
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
TL;DR: In this paper, the authors proposed a novel "simultaneous logic in-memory" (SLIM) methodology that allows to implement both memory and logic operations simultaneously on the same bitcell in a non-destructive manner without losing the previously stored Memory state.
Journal ArticleDOI
Dual-configuration in-memory computing bitcells using SiOx RRAM for binary neural networks
Sandeep Kaur Kingra,Vivek Parmar,Shubham Negi,Alessandro Bricalli,G. Piccolboni,Amir Regev,J. F. Nodin,G. Molas,Manan Suri +8 more
TL;DR: In this paper , a dual-configuration XNOR (exclusive NOR) IMC bitcell is realized using fabricated 1T-1R SiOx RRAM (resistive random access memory) arrays.
Proceedings ArticleDOI
Hybrid CMOS-OxRAM based 4T-2R NVSRAM with efficient programming scheme
TL;DR: This paper presents an OxRAM based compact 4T-2R NVSRAM design with a novel efficient programming scheme to achieve low-power and low area footprint and shows that by carefully choosing the OxRAM programmed resistance levels the pull-down NMOS transitor size, andNVSRAM programming energy can be further reduced by a factor of 3x and 4x respectively.
Journal ArticleDOI
Programming scheme based optimization of hybrid 4T-2R OxRAM NVSRAM
TL;DR: The proposed single-cycle, parallel RRAM device programming scheme coupled with the 4T-2R architecture leads to several benefits such as- possibility of unconventional transistor sizing, 50% lower latency, 20% improvement in SNM and ~20× reduced energy requirements, when compared against two-cycle programming approach.