There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Early dark energy (EDE) that behaves like a cosmological constant at early times (redshifts z≳3000) and then dilutes away like radiation or faster at later times can solve the Hubble tension. In these models, the sound horizon at decoupling is reduced resulting in a larger value of the Hubble parameter H_{0} inferred from the cosmic microwave background (CMB). We consider two physical models for this EDE, one involving an oscillating scalar field and another a slowly rolling field. We perform a detailed calculation of the evolution of perturbations in these models. A Markov Chain Monte Carlo search of the parameter space for the EDE parameters, in conjunction with the standard cosmological parameters, identifies regions in which H_{0} inferred from Planck CMB data agrees with the SH0ES local measurement. In these cosmologies, current baryon acoustic oscillation and supernova data are described as successfully as in the cold dark matter model with a cosmological constant, while the fit to Planck data is slightly improved. Future CMB and large-scale-structure surveys will further probe this scenario.

/pdf/early-dark-energy-can-resolve-the-hubble-tension-13pxyq2mp9.pdf

Early Dark Energy can Resolve the Hubble Tension.

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

Solid-state electronics

A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.

Nand flash memory array with cut-off gate line and methods for operating and fabricating the same

Group-IV materials for monolithic integration with silicon optoelectronic systems are being extensively studied. As a part of efforts, light emission from germanium has been pursued with the objective of evolving germanium into an efficient light source for optical communication systems. In this study, we demonstrate room-temperature electroluminescence from germanium in an Al0.3Ga0.7As/Ge heterojunction light-emitting diode without any complicated manipulation for alternating material properties of germanium. Electroluminescence peaks were observed near 1550 nm and the energy around this wavelength corresponds to that emitted from direct recombination at the Γ-valley of germanium.

Room-temperature electroluminescence from germanium in an Al 0.3 Ga 0.7 As/Ge heterojunction light-emitting diode by Γ-valley transport

In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming voltage is realized by inserting the SiGe QW beside the drain. This QW also functions as the storage node, which enhances not only the current sensing margin but also the retention time ( $\tau _{{\text {ret}}}$ ) compared with those of all-Si device. At an extremely scaled cell size and sub-10-ns write/erase operations, the proposed device shows 0.2-s-long $\tau _{{\text {ret}}}$ and current ratio > 104. It has been verified that a single cycle of 1T DRAM operations consumes only 93.8 fJ.

A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency

In this paper, arch gate silicon–oxide–nitride–oxide–silicon (SONOS) flash memory is studied. The key technology for this device lies in making the device channel on an arch-shaped silicon fin. This feature enhances the electric field across the tunneling oxide by field concentration, and at the same time, reduces the field across the barrier oxide. Thus, when the high gate voltage is applied in the program operation, the tunneling current, and in turn, the program speed is drastically improved. The lowered electric field at the top oxide prohibits the electron back-tunneling from the polycrystalline silicon gate, which enables more reliable and faster erase operation. Full fabrication processes and the measurement results are presented in detail. The process and device simulation results are also given to confirm the critical electrostatic characteristics of the Arch SONOS flash memory device at each step and design the process integration.

https://iopscience.iop.org/article/10.1143/JJAP.49.114202/pdf

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

In this paper, we present the radiofrequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-㎚ channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 ㎔. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of Y₂₂-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.

http://www.koreascience.or.kr:80/article/JAKO201220962915935.pdf

Seongjae Cho

Papers

Nand flash memory array with cut-off gate line and methods for operating and fabricating the same

Room-temperature electroluminescence from germanium in an Al 0.3 Ga 0.7 As/Ge heterojunction light-emitting diode by Γ-valley transport

A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications