In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to $\sim 50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

Tunnel Field-Effect Transistor With an L-Shaped Gate

In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V
 g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V
 g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

/pdf/design-of-high-performance-si-sige-heterojunction-tunneling-2q82srnoqv.pdf

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate

In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (ION) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s ION and switching ratio (ION/IOFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (Vg). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V Vg) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V Vg) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (gm), output conductance (gds), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (Vd), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications.

/pdf/analog-rf-performance-of-t-shape-gate-dual-source-tunnel-2dbuakvmk7.pdf

Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon on insulator. The proposed Schottky device employs a dual material at the source side and is being named as the source engineered SB MOSFET (SE-SB-MOSFET). Erbium silicide (ErSi1.7) is used as the main source material, and Hafnium is used as a source extension. The use of Hafnium as a source extension induces an n+-type charge plasma in an undoped silicon film, which significantly reduces the SB thickness. A calibrated simulation study has shown that the ON current ( $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}$ ) and $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}/I_{{{\mathrm{{\scriptscriptstyle OFF}}}}}$ have increased by 225 and $65\times $ , respectively, in the proposed device in comparison with the conventional SB-MOSFET device. The ac analysis has shown that the cutoff frequency ( $f_{T}$ ) in the proposed SE-SB-MOSFET ( $\sim 200$ GHz) has increased by $200\times $ as compared with the conventional SB-MOSFET ( $\sim 1$ GHz). Furthermore, the performance of the proposed device has been tested at the circuit level also. It has been observed from the transient analysis that a significant reduction in switching ON delay ( $65\times $ ) and switching OFF delay (33%) has been achieved in the proposed SE-SB-MOSFET-based inverter in comparison with the conventional device-based inverter. Furthermore, the use of the charge plasma concept makes the fabrication of the proposed device relatively easy as it uses low thermal budget.

A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI

This study presents a reversible, mediatorless, near-infrared glucose sensor based on glucose oxidase-wrapped SWCNTs. A combination of fluorescence, absorption, and Raman spectroscopy measurements suggest a fluorescence enhancement mechanism based on localized enzymatic doping of SWCNT defect sites that does not rely on added mediators. The cyclic addition and removal of glucose is shown to enhance and recover fluorescence, demonstrating reversibility.

Mediatorless, Reversible Optical Nanosensor Enabled through Enzymatic Pocket Doping.

A tunnel field-effect transistor (FET) (TFET), in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub-0.6-V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer-drain overlap on the device characteristics of such silicon TFET is reported in this paper. It is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current IOFF can be achieved by appropriate designing of the spacer-drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel-resistance limited region results in long-channel metal-oxide-semiconductor FET-like output characteristics for such a structure. Short-channel effects, such as drain-induced barrier lowering, are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported.

Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

It is known that a pocket at the drain end of a Schottky barrier tunneling FET (SB-TFET) helps to improve the device performance in terms of greatly suppressed ambipolar current and reduced drain-induced barrier lowering (DIBL) A detailed investigation, with the help of a numerical device simulator, of the impact of using such a pocket either at the source end or at both the source and the drain ends of an SB-TFET is reported for the first time in this paper The performance of the above-mentioned two devices is compared with a device having a pocket at the drain end and a conventional MOSFET Optimization of the barrier height and the pocket parameters is made before performance comparison It is observed that a pocket at the drain end helps suppress the ambipolar current and reduce both the subthreshold swing and the DIBL On the other hand, a pocket at the source end helps to improve the ON-state current $I_{\mathrm{{\scriptstyle ON}}}$  Using a pocket at both the source and the drain ends results in overall improvement of the device performance The effects of scaling on such device performance parameters are also reported

Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor

In this paper, we report the logic performance of CMOS circuits implemented with n- and p-channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made between such circuits and those implemented with n- and p-channel conventional inversion-mode (IM) FinFETs. The logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators. Frequency of oscillation of a three-stage ring oscillator (RO) is also obtained for such nodes. In spite of reduced ON-state current arising out of the higher channel doping and, hence, reduced carrier mobility in the JL devices, somewhat improved performance of the JL CMOS circuits over their IM counterparts are observed. For example, improvement of ~28% and ~10% in the rise time and fall time, respectively, for the inverter and ~12% in the frequency of oscillation of RO are observed for 10-nm technology node. Our investigations reveal reduced gate capacitance of the JL devices that in turn result in such improved performance of the JL CMOS circuits. Reduced gate capacitance also results in reduced dynamic power dissipation of JL CMOS circuits.

Comparison of Logic Performance of CMOS Circuits Implemented With Junctionless and Inversion-Mode FinFETs

In this paper, we report an investigation of the performance of a Ge junctionless (JL) p-FinFET and compare it with that of a Si JL p-FinFET for logic applications. CMOS inverters are built with such Ge p-FinFETs and Si n-FinFETs for three different technology nodes as per the ITRS roadmap. Transient analysis of CMOS inverters is made to evaluate the logic performance parameters such as rise time and fall time. Then, mixed-mode circuit simulations are performed for a three-stage ring oscillator, build with such CMOS inverters, to evaluate frequency of oscillation and propagation delay. Our investigations reveal that CMOS circuits built with Ge JL p-FinFETs outperform their equally sized all Si counterpart. Reduction of ~ 70% in the rise time for the CMOS inverters and improvement of more than 75% in the frequency of oscillation for the ring oscillators are observed for all three technology nodes when Ge p-channel devices are used.

Performance of Ge p-channel junctionless FinFETs for logic applications

In this paper, a detailed investigation of the impact of using a pocket in a Schottky-barrier tunneling FET (SBTFET) is reported. It is found that a pocket at both the source and the drain ends results in overall improvement of the device performance.

Shilpi Guin

Papers

Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor

Comparison of Logic Performance of CMOS Circuits Implemented With Junctionless and Inversion-Mode FinFETs

Performance of Ge p-channel junctionless FinFETs for logic applications

Influence of a pocket doping in a Schottky tunneling FET