Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

https://opus.lib.uts.edu.au/bitstream/10453/14761/1/2010005083.pdf

Arsenic accumulation in rice (Oryza sativa L.): Human exposure through food chain

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency $f_{{T}}$ , maximum oscillation frequency $f_{\max}$ , transconductance frequency product, higher order transconductance coefficients $({g}_{{m}1}, {g}_{{m}3})$ , VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HD-GAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

In this paper, a short-gate tunneling-field-effect-transistor (SG-TFET) structure has been investigated for the dielectrically modulated biosensing applications in comparison with a full-gate tunneling-field-effect-transistor structure of similar dimensions. This paper explores the underlying physics of these architectures and estimates their comparative sensing performance. The sensing performance has been evaluated for both the charged and charge-neutral biomolecules using extensive device-level simulation, and the effects of the biomolecule dielectric constant and charge density are also studied. In SG-TFET architecture, the reduction of the gate length enhances its drain control over the band-to-band tunneling process and this has been exploited for the detection, resulting to superior drain current sensitivity for biomolecule conjugation. The gate and drain biasing conditions show dominant impact on the sensitivity enhancement in the short-gate biosensors. Therefore, the gate and drain bias are identified as the effective design parameters for the efficiency optimization.

Comparative Performance Analysis of the Dielectrically Modulated Full- Gate and Short-Gate Tunnel FET-Based Biosensors

In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to $\sim 50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

Tunnel Field-Effect Transistor With an L-Shaped Gate

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO, intrinsic gain, and unity-gain cutoff frequency fT, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although gm is lower, gm/ID is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high RO and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET.

Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-m/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide semiconductor field-effect transistor, particularly for low-power applications It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages

Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

A tunnel field-effect transistor (FET) (TFET), in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub-0.6-V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer-drain overlap on the device characteristics of such silicon TFET is reported in this paper. It is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current IOFF can be achieved by appropriate designing of the spacer-drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel-resistance limited region results in long-channel metal-oxide-semiconductor FET-like output characteristics for such a structure. Short-channel effects, such as drain-induced barrier lowering, are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported.

Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

This letter reports, for the first time, the performance of a junctionless (JL) FinFET in the presence of random grain orientation-induced metal workfunction variability (WFV), as compared with a similarly sized conventional FinFET. Relative impact of random discrete dopant (RDD)-induced variability and WFV are also compared between such devices by the use of a 3-D numerical device simulator. Numerical values of standard deviation of different device parameters reveal that the performance parameters of a JL FinFET are significantly affected by WFV. In addition, the impact of the RDD, as compared with WFV, is larger in JL devices, as expected.

Avik Chattopadhyay

Papers

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

Comparison of Random Dopant and Gate-Metal Workfunction Variability Between Junctionless and Conventional FinFETs