This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

https://iopscience.iop.org/article/10.1088/2057-1976/ab1674/pdf

Design considerations for effective neural signal sensing and amplification: a review

In this paper, a method of realizing voltage-mode (VM) non-inverting high-pass filter (HPF), band-pass filter (BPF), low-pass filter (LPF), and inverting low-pass filter (ILPF) transfer functions structure with two grounded capacitors and four resistors through an analytical synthesis method is presented. The synthesis structure of the VM biquadratic filter consists of a voltage proportional block and two voltage lossless integrators based on the use of current feedback operational amplifiers (CFOAs). It is demonstrated that the derived biquadratic filter structure can simultaneously realize VM HPF, BPF and ILPF transfer functions or VM BPF and LPF transfer functions at a high-input impedance terminal. The VM biquadratic filter can independently adjust the resonance angular frequency and quality factor. By slightly modifying the proposed biquadratic filter, a VM quadrature sinusoidal oscillator can be achieved. The proposed biquadratic filter and quadrature oscillator have been simulated by OrCAD PSpice and appropriate hardware has been implemented with AD844-type CFOAs. In order to reduce power consumption, reduce chip area, reduce costs, and improve system integration, integrated VM CFOA-based biquadratic filter circuits and quadrature oscillator circuits are very important. The proposed filter and quadrature oscillator have been further fabricated in $0.18~\mu \text{m}$ 1P6M CMOS process technology. The entire chip area is 0.974 mm2, including a filter chip cell and an oscillator chip cell. Under the supply voltage of ±0.9 V, the total power dissipation of the filter chip cell is 5.4 mW, and the figure-of-merit (FOM) of filter chip cell is 66.7%. The measured value of the third-order intermodulation distortion of the filter chip cell is −55.29 dBc and the third-order intercept point is 19.9 dBm. The measured phase noise of CFOA-based filter chip cell at 1 kHz offset is less than −99.76 dBc/Hz.

/pdf/analytical-synthesis-of-high-pass-band-pass-and-low-pass-1suky3y4xp.pdf

Analytical Synthesis of High-Pass, Band-Pass and Low-Pass Biquadratic Filters and its Quadrature Oscillator Application Using Current-Feedback Operational Amplifiers

Closed-loop neural recording requires a front-end with a wide DR to record small neural signals without distortion in the presence of a DC electrode offset (~50mV) and a large stimulation artifact (~ 200mV pp ). To remove DC offset, a conventional architecture uses an AC-coupled LNA and a subsequent ADC [1]. However, to realize a small HPF cut-off frequency ( 80dB), a large linear operating range (>250mV), a high DC input impedance (>1GΩ), and a large common-mode rejection (>70dB). Fulfilling all these requirements often leads to ADCs with poor energy-efficiency [2], [3]. This paper presents a continuous-time delta-sigma modulator (CT-ALM) with G m -input for closed-loop neural recording. It achieves a high input impedance, 300mV pp linear input range, 80.4dB SNDR, and 76dB CMRR, and consumes only 6.5μW with a signal bandwidth of 10kHz. This corresponds to a 172.3dB FOM.

26.6 A 6.5µW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with G m -Input and 300mV pp Linear Input Range for Closed-Loop Neural Recording

Monitoring the electrical neural signals is an important method for understanding the neuronal mechanism. In particular, in order to perform a cell-type-specific study, it is necessary to observe the concentration of calcium ions using fluorescent indicators in addition to measuring the electrical neural signal. This paper presents a multimodal multichannel neural activity readout integrated circuit that can perform not only electrical neural recording but also fluorescence recording of neural activity for the cell-type-specific study of heterogeneous neuronal cell populations. For monitoring the calcium ions, the photodiode generates the current according to the fluorescence expressed by the reaction between the genetically encoded calcium indicators and calcium ions. The time-based fluorescence recording circuit then records the photodiode current. The electrical neural signal captured by the microelectrode is recorded through the low-noise amplifier, variable gain amplifier, and analog-to-digital converter. The proposed integrated circuit is fabricated in a 1-poly 6-metal (1P6M) 0.18- $\mu \text{m}$ CMOS process. The fluorescence recording circuit achieves a recording range of 81 dB (75 pA to 860 nA) and consumes a power of 724 nW/channel. The electrical recording circuit achieves an input-referred noise of $2.7~\mu \text{V}_{\mathrm {rms}}$ over the bandwidth of 10 kHz, while consuming the power of $4.9~\mu \text{W}$ /channel. The functionality of the proposed circuits is verified through the in vivo and in vitro experiments. Compared to the conventional neuroscience tools, which consist of bulky off-chip components, this neural interface is implemented in a compact size to perform multimodal neural recording while consuming low power.

/pdf/a-multimodal-neural-activity-readout-integrated-circuit-for-81sbwd109h.pdf

A Multimodal Neural Activity Readout Integrated Circuit for Recording Fluorescence and Electrical Signals

This paper presents an ultra-low-power receiver based on the injection-locked oscillator (ILO), which is compatible with multiple modulation schemes such as on-off keying (OOK), binary frequency-shift keying (BFSK), and differential binary phase-shift keying (DBPSK). The receiver has been fabricated in 0.18- $\mu \text{m}$ CMOS technology and operates in the ISM band of 2.4 GHz. A simple envelope detection can be used even for the demodulation of BFSK and DBPSK signals due to the conversion capability of the ILO from the frequency and phase to the amplitude. In the proposed receiver, a $Q$ -enhanced single-ended-to-differential amplifier is employed to provide high-gain amplification as well as narrow band-pass filtering, which improves the sensitivity and selectivity of the receiver. In addition, a gain-control loop is formed in the receiver to maintain constant lock range and hence frequency-to-amplitude conversion ratio for the varying power of the BFSK-modulated receiver input signal. The receiver achieves the sensitivity of −87, −85, and −82 dBm for the OOK, BFSK, and DBPSK signals respectively at the data rate of 50 kb/s and the BER lower than 0.1% while consuming the power of $324~\mu \text{W}$ in total.

/pdf/a-multi-mode-ulp-receiver-based-on-an-injection-locked-1fwb67w0ts.pdf

A Multi-Mode ULP Receiver Based on an Injection-Locked Oscillator for IoT Applications

Long-term neural recording which can consistently provide good signal-to-noise ratio (SNR) performance over time is important for stable operation of neuroprosthetic systems. This paper presents an analysis for the SNR optimization in a changing environment which causes variations in the tissue-electrode impedance, Zte. Based on the analysis result, a neural recording amplifier (NRA) is developed employing the SNR optimization technique. The NRA can adaptively change its configuration for in situ SNR optimization. The SNR is improved by 4.69% to 23.33% as Zte changes from 1.59 MQ to 31.8 MQ at 1 kHz. The NRA is fabricated in a 0.18-μm standard CMOS process and operates at 1.8-V supply while consuming 1.6 μA It achieves an input-referred noise of 4.67 μVrms when integrated from 1 Hz to 10 kHz, which leads to the NEF of 2.27 and the NEF2VDD of 9.28. The frequency reponse is measured with a high-pass cutoff frequency of 1 Hz and a low-pass cutoff frequency of 10 kHz. The midband gain is set to 40 dB while occupying 0.11 mm2 of a chip area.

A neural recording amplifier based on adaptive SNR optimization technique for long-term implantation

This paper presents a 5-bit VCO-based neural recording IC, which directly quantizes the input signal and achieves a large dynamic range (DR) to process the small-amplitude neural signal in the presence of the large-amplitude stimulation artifact (SA). A feedback-controlled source degeneration is applied to the input transconductor circuit (Gm,in) by using a resistor DAC (R-DAC). It mitigates the circuit nonlinearity, resulting in a large signal-to-noise-and-distortion ratio (SNDR) and a high input impedance (Z in ). The implemented neural recording IC achieves 813dB SNDR over 200Hz signal bandwidth and 200mV PP maximum allowable input range while consuming 3.9μW per channel.

A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS

This paper presents a fully differential implantable neural recording front-end IC for monitoring neural activities. Each analog front-end (AFE) consists of a low-noise amplifier (LNA), a variable gain amplifier (VGA), and a buffer. The output signal of the AFE is digitized through a successive approximation register analog-to-digital converter (SAR ADC). The LNA adopts the currentreuse technique to improve the current efficiency, achieving the power consumption as low as 0.95 μW. The implemented LNA has the gain of 40 dB, the lowpass cutoff frequency of 10 kHz, and the high-pass cutoff frequency of sub-1 Hz which is realized using the current-controlled pseudoresistor. The VGA controls the gain from 21.9 dB to 33.9 dB for efficient digitization while consuming the power of 0.35 μW. The buffer drives the capacitive DAC of the ADC and consumes the power of 3.28 μW. The fabricated AFE occupies the area of 0.11 ㎟/Channel and consumes 4.6 μW/Channel under 1-V supply voltage. Each channel achieves the input-referred noise of 2.88 μVrms, the NEF of 2.38, and the NEF²VDD of 5.67. The front-end IC is implemented in a standard 1P6M 0.18-mm CMOS process.

A 1-V 4.6-μW/channel Fully Differential Neural Recording Front-end IC with Current-controlled Pseudoresistor in 0.18-μm CMOS

This paper presents an ultra-low power, low cost demodulator for gaussian frequency shift keying (GFSK) receivers that use low intermediate frequencies (IF). The demodulator employs a direct IF to digital data conversion scheme by using an injection-locked ring oscillator (ILRO) with a 1-bit flip-flop. It consumes $2.7~\mu \text{W}$ from a 1.0 V supply at a data rate of 500 kbps achieving an energy efficiency of 5.4 pJ/bit which is 30 times better than that of the recently presented works. The demodulator also achieves 17.5 dB SNR at 0.1 % BER while operating at the same date rate. The demodulator is implemented in a $0.18~\mu \text{m}$ standard CMOS process and occupies an active area of 0.012 mm2.

/pdf/a-1-0-v-5-4-pj-bit-gfsk-demodulator-based-on-an-injection-1sq5fw1wz8.pdf

Soonyoung Hong

Papers

A Multi-Mode ULP Receiver Based on an Injection-Locked Oscillator for IoT Applications

A neural recording amplifier based on adaptive SNR optimization technique for long-term implantation

A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS

A 1-V 4.6-μW/channel Fully Differential Neural Recording Front-end IC with Current-controlled Pseudoresistor in 0.18-μm CMOS

A 1.0 V, 5.4 pJ/bit GFSK Demodulator Based on an Injection Locked Ring Oscillator for Low-IF Receivers