Showing papers by "Souvik Mahapatra published in 2001"

Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs

Abstract: Sensitive quantum-yield measurements (M) on n-channel MOSFETs for drain voltages (V/sub D/) near the bandgap voltage of silicon, showed an abnormal bell-shaped M versus gate voltage (V/sub G/) characteristic at 77 K. At higher V/sub D/, M decreases monotonously with increasing V/sub G/. Measured data is interpreted based on the general nature of electron energy distribution published by Monte-Carlo simulation groups and provide simultaneous experimental verification for the presence of a tail that depends strongly on lattice temperature and electron-electron interaction (EEI) broadening of the tail. Our data suggest EEI broadening of the tail even in the subthreshold regime.

A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique

Abstract: The spatial distribution of interface traps in hot-carrier stressed lateral asymmetric channel (LAC) and conventional (CON) MOSFETs have been determined using a novel charge pumping technique. Detailed post-stress interface characterization shows reduced interface-trap buildup and lesser drain current degradation in LAC MOSFETs compared to the CON device, for stressing at different times and drain biases and for all channel lengths down to 100 nm. The interface-trap profile parameters (peak magnitude and spread) have been correlated to drain current degradation as function of stress drain bias and time. It is shown that with increased stress drain bias and time, both the peak and spread of the interface-trap profiles increase, but at different rates. While the peaks evolve identically for CON and LAC MOSFETs, the spreads do not, which is shown to affect the rate of the resulting transconductance degradation differently. Device simulations show a lower peak lateral electric field in LAC MOSFETs compared to CON devices, which is responsible for the observed reduction in hot-carrier degradation in such devices.

Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering

Abstract: A comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D/sup 2/FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime.

Study of Degradation in Channel Initiated Secondary Electron Injection Regime

Abstract: This paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current (IB) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias.

Comparison of Sub-Bandgap Impact Ionization in Sub-100 nm Conventional and Lateral Asymmetrical Channel nMOSFETs

Abstract: Sub-bandgap impact ionization is compared in 100 nm channel length conventional channel and laterally asymmetrical n-channel metal oxide semiconductor field effect transistor (MOSFET). An abnormal increase of the gate voltage at which the substrate current peaks is reported. The effect is enhanced in the case of laterally asymmetric channel devices. Experimental and simulation results are presented that suggest the role of inversion layer quantization as an energy gain mechanism.

Observation of double peak in the substrate current versus gate voltage characteristics of n-channel metal-oxide-semiconductor field effect transistors

Abstract: By employing sensitive current measurements at low drain voltages for n-channel metal–oxide–semiconductor field effect transistors with different channel dopings, substrate current versus gate voltage characteristics with two peaks were obtained for devices with low channel doping at 77 K. This differs from the single peak bell shaped curves reported in the literature. The data are analyzed and suggest that the second peak is due to the contribution of electron–electron interactions to the high energy tail of the electron energy distribution. Indirect contributions by the thermal tail of the electron energy distribution and ionized impurity scattering that make the second peak visible are also discussed.