An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Emerging challenges and materials for thermal management of electronics

An electrical plug and receptacle relying on magnetic force from an electromagnet to maintain contact are disclosed. The plug and receptacle can be used as part of a power adapter for connecting an electronic device, such as a laptop computer, to a power supply. The plug includes electrical contacts, which are preferably biased toward corresponding contacts on the receptacle. The plug and receptacle each have a magnetic element. The magnetic element on one of the plug or receptacle can be a magnet or ferromagnetic material. The magnetic element on the other of the plug or receptacle is an electromagnet. When the plug and receptacle are brought into proximity, the magnetic attraction between the electromagnet magnet and its complement, whether another magnet or a ferromagnetic material, maintains the contacts in an electrically conductive relationship.

Magnetic connector for electronic device

A surface cleaning apparatus comprises a body including a rear compartment, a forward compartment and an intermediate compartment arranged between the rear and forward compartments. An elongate rotatable brush arrangement is positioned within and extends across the forward compartment. An electric motor is positioned in the rear compartment, and drive means extends between the rotatable brush arrangement and the electric motor.

Surface cleaning apparatus

The depletion of the world's limited reservoirs of fossil fuels, the worldwide impact of global warming and the high cost of energy are among the primary issues driving a renewed interest in the capture and reuse of waste energy. A major source of waste energy is being created by data centers through the increasing demand for cloud based connectivity and performance. In fact, recent figures show that data centers are responsible for more than 2% of the US total electricity usage. Almost half of this power is used for cooling the electronics, creating a significant stream of waste heat. The difficulty associated with recovering and reusing this stream of waste heat is that the heat is of low quality. In this paper, the most promising methods and technologies for recovering data center low-grade waste heat in an effective and economically reasonable way are identified and discussed. A number of currently available and developmental low-grade waste heat recovery techniques including district/plant/water heating, absorption cooling, direct power generation (piezoelectric and thermoelectric), indirect power generation (steam and organic Rankine cycle), biomass co-location, and desalination/clean water are reviewed along with their operational requirements in order to assess the suitability and effectiveness of each technology for data center applications. Based on a comparison between data centers' operational thermodynamic conditions and the operational requirements of the discussed waste heat recovery techniques, absorption cooling and organic Rankine cycle are found to be among the most promising technologies for data center waste heat reuse.

A review of data center cooling technology, operating conditions and the corresponding low-grade waste heat recovery opportunities

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

Three-dimensional silicon integration

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

A method to forecast the energy sources and energy sinks to facilitate continuous capacity planning, regulation and control of energy state of an entity under variable weather condition is established. Energy sources of specific focus are related to renewable energy forms from wind, solar and wave that are highly dependent on prevailing weather conditions.

Smarter-grid: method to forecast electric energy production and utilization subject to uncertain environmental variables

A method (and system) of predicting a thermal state of a transient thermal system, includes combining sensor outputs and thermal parameters to construct a consistent set of estimates of internal temperature of a transient thermal system.

Method and system for real-time estimation and prediction of the thermal state of a microprocessor unit

An electrical cable for a portable computer includes a plurality of electrical leads bound together in a flexible sheath. A first snap connector is joined to the leads. A second snap connector is complementary to the first snap connector and is connected thereto for establishing electrical connection with the computer, and allowing self-disconnection thereof upon yanking of the cable over a range of angles relative to the computer including a hemisphere.

Sri M. Sri-Jayantha

Papers

Three-dimensional silicon integration

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Smarter-grid: method to forecast electric energy production and utilization subject to uncertain environmental variables

Method and system for real-time estimation and prediction of the thermal state of a microprocessor unit

Safe-snap computer cable