Leena Paivikki Buchwalter

TL;DR: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is more than or close to the substrate.

TL;DR: The technical challenges and recent progress made in the development of silicon carrier technology for potential new applications are described.

TL;DR: In this paper, a method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed.

TL;DR: In this article, the authors discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example, and discuss a silicon carrier package technology with fine pitch (50 mum) interconnection.

TL;DR: In this article, a method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented.