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Robert J. Polastre
Researcher at IBM
Publications - 59
Citations - 3066
Robert J. Polastre is an academic researcher from IBM. The author has contributed to research in topics: Interconnection & Chip. The author has an hindex of 25, co-authored 59 publications receiving 2959 citations. Previous affiliations of Robert J. Polastre include GlobalFoundries.
Papers
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Journal ArticleDOI
Three-dimensional silicon integration
John U. Knickerbocker,P.S. Andry,B. Dang,R. Horton,Mario J. Interrante,Chirag S. Patel,Robert J. Polastre,Katsuyuki Sakuma,R. Sirdeshmukh,Edmund J. Sprogis,Sri M. Sri-Jayantha,A. M. Stephens,Anna W. Topol,Cornelia K. Tsang,B. C. Webb,Steven L. Wright +15 more
TL;DR: 3D technology from IBM is highlighted, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and examples of 3D emerging industry product applications that could create marketable systems are provided.
Journal ArticleDOI
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
John U. Knickerbocker,P.S. Andry,Leena Paivikki Buchwalter,Alina Deutsch,R. Horton,Keith A. Jenkins,Young H. Kwark,Gerard McVicker,Chirag S. Patel,Robert J. Polastre,Christian Schuster,Arun Sharma,Sri M. Sri-Jayantha,C.W. Surovic,Cornelia K. Tsang,Bucknell C. Webb,Steven L. Wright,Samuel McKnight,Edmund J. Sprogis,B. Dang +19 more
TL;DR: The technical challenges and recent progress made in the development of silicon carrier technology for potential new applications are described.
Proceedings ArticleDOI
3D silicon integration
John U. Knickerbocker,P.S. Andry,B. Dang,R. Horton,Chirag S. Patel,Robert J. Polastre,Katsuyuki Sakuma,E.S. Sprogis,Cornelia K. Tsang,B. C. Webb,Steven L. Wright +10 more
TL;DR: In this article, the authors describe recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures, as well as examples of potential applications that may take advantage of 3D integration are discussed.
Journal ArticleDOI
A Practical Implementation of Silicon Microchannel Coolers for High Power Chips
Evan G. Colgan,Bruce K. Furman,Michael A. Gaynes,W. Graham,Nancy C. LaBianca,John H. Magerlein,Robert J. Polastre,M.B. Rothwell,Raschid J. Bezama,Rehan Choudhary,Kenneth C. Marston,Hilton T. Toy,Jamil A. Wakil,Jeffrey A. Zitz,Roger R. Schmidt +14 more
TL;DR: In this paper, the authors describe a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors, which is able to cool chips with average power densities of 400W/cm2 or more.
Proceedings ArticleDOI
A practical implementation of silicon microchannel coolers for high power chips
Evan G. Colgan,Bruce K. Furman,A. Gaynes,W. Graham,Nancy C. LaBianca,John H. Magerlein,Robert J. Polastre,M.B. Rothwell,Raschid J. Bezama,Rehan Choudhary,Kenneth C. Marston,Hilton T. Toy,Jamil A. Wakil,Jeffrey A. Zitz +13 more
TL;DR: In this article, the authors describe a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors, achieving a unit thermal resistance of 10.5 C-mm/sup 2/W from the cooler surface to the inlet water with a fluid pressure drop of less than 35 kPa.