S
Sébastien Barnola
Researcher at Commissariat à l'énergie atomique et aux énergies alternatives
Publications - 98
Citations - 1759
Sébastien Barnola is an academic researcher from Commissariat à l'énergie atomique et aux énergies alternatives. The author has contributed to research in topics: Etching (microfabrication) & Silicon on insulator. The author has an hindex of 21, co-authored 98 publications receiving 1625 citations. Previous affiliations of Sébastien Barnola include STMicroelectronics & University of Grenoble.
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Proceedings ArticleDOI
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
O. Faynot,Francois Andrieu,Olivier Weber,Claire Fenouillet-Beranger,Pierre Perreau,J. Mazurier,T. Benoist,O. Rozeau,Thierry Poiroux,Maud Vinet,Laurent Grenouillet,J.-P. Noel,Nicolas Posseme,Sébastien Barnola,François Martin,C. Lapeyre,Mikael Casse,X. Garros,M-A. Jaud,Olivier P. Thomas,G. Cibrario,L. Tosti,L. Brevard,Claude Tabone,P. Gaud,Sylvain Barraud,Thomas Ernst,Simon Deleonibus +27 more
TL;DR: In this article, the main advantages of planar undoped channel Fully depleted SOI devices are discussed and solutions to the Multiple V T challenges and non logic devices (ESD, I/Os) are reported.
Journal ArticleDOI
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below
Claire Fenouillet-Beranger,Stephane Denorme,Pierre Perreau,C. Buj,O. Faynot,Francois Andrieu,L. Tosti,Sébastien Barnola,T. Salvetat,X. Garros,Mikael Casse,F. Allain,Nicolas Loubet,Loan Pham-Nguyen,E. Deloffre,Mickael Gros-Jean,Remi Beneyton,C. Laviron,M. Marin,C. Leyris,Sebastien Haendler,Francois Leverd,Pascal Gouraud,P. Scheiblin,L. Clement,Roland Pantel,Simon Deleonibus,Thomas Skotnicki +27 more
TL;DR: In this article, the authors compared Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP) conditions and compared them with bulk 45-nm technology in terms of variability and noise.
Proceedings ArticleDOI
15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET
Cecilia Dupre,Arnaud Hubert,S. Becu,M. Jublot,V. Maffini-Alvaro,C. Vizioz,F. Aussenac,Christian Arvet,Sébastien Barnola,J.M. Hartmann,G. Garnier,F. Allain,J. P. Colonna,Maurice Rivoire,L. Baud,S. Pauliac,Virginie Loup,Thierry Chevolleau,P. Rivallin,Bernard Guillaumot,Gerard Ghibaudo,O. Faynot,Thomas Ernst,Simon Deleonibus +23 more
TL;DR: In this paper, a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET is reported.
Proceedings ArticleDOI
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
Francois Andrieu,Olivier Weber,J. Mazurier,Olivier P. Thomas,J.-P. Noel,Claire Fenouillet-Beranger,J-P. Mazellier,Pierre Perreau,Thierry Poiroux,Yves Morand,T. Morel,S. Allegret,Virginie Loup,Sébastien Barnola,François Martin,J.-F. Damlencourt,I. Servin,M. Casse,X. Garros,O. Rozeau,M-A. Jaud,G. Cibrario,J. Cluzel,Alain Toffoli,F. Allain,R. Kies,D. Lafond,Vincent Delaye,Claude Tabone,L. Tosti,L. Brevard,P. Gaud,Vamsi Paruchuri,Konstantin Bourdelle,Walter Schwarzenbach,O. Bonnin,By. Nguyen,Bruce B. Doris,Frederic Boeuf,Thomas Skotnicki,O. Faynot +40 more
TL;DR: In this paper, the authors used a single mid-gap gate stack to produce 6T-SRAM cells with good characteristics down to V DD = 0.5V supply voltage and with excellent SNM dispersion across the wafer.
Proceedings ArticleDOI
Efficient multi-V T FDSOI technology with UTBOX for low power circuit design
C. Fenouillet-Beranger,Olivier P. Thomas,P. Perreau,J.-P. Noel,A. Bajolet,Sebastien Haendler,L. Tosti,Sébastien Barnola,Remi Beneyton,C. Perrot,C. de Buttet,F. Abbate,F. Baron,B. Pernet,Y. Campidelli,L. Pinzelli,Pascal Gouraud,M. Casse,C. Borowiak,Olivier Weber,Francois Andrieu,Konstantin Bourdelle,Bich-Yen Nguyen,F. Boedt,Stephane Denorme,Frederic Boeuf,O. Faynot,Thomas Skotnicki +27 more
TL;DR: For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated and the effectiveness of back biasing for short devices in order to achieve I-ON current improvement by 45% for LVT options at an I-OFF current of 23nA/µm and a leakage reduction by 2 decades.