M
Mickael Gros-Jean
Researcher at STMicroelectronics
Publications - 59
Citations - 1116
Mickael Gros-Jean is an academic researcher from STMicroelectronics. The author has contributed to research in topics: High-κ dielectric & Atomic layer deposition. The author has an hindex of 16, co-authored 57 publications receiving 1011 citations.
Papers
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Proceedings ArticleDOI
A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz f T / 370 GHz f MAX HBT and high-Q millimeter-wave passives
Pascal Chevalier,G. Avenier,G. Ribes,A. Montagne,E. Canderle,Didier Celi,N. Derrier,C. Deglise,Cedric Durand,Thomas Quemerais,M. Buczko,Daniel Gloria,O. Robin,Sébastien Petitdidier,Y. Campidelli,F. Abbate,Mickael Gros-Jean,L. Berthier,Jean-Damien Chapon,Francois Leverd,C. Jenny,C. Richard,Olivier Gourhant,C. De-Buttet,Remi Beneyton,Patrick Maury,S. Joblot,Laurent Favennec,M. Guillermet,P. Brun,K. Courouble,K. Haxaire,G. Imbert,E. Gourvest,J. Cossalter,O. Saxod,Clement Tavernier,F. Foussadier,B. Ramadout,R. Bianchini,C. Julien,D. Ney,Julien Rosa,Sebastien Haendler,Y. Carminati,B. Borot +45 more
TL;DR: In this paper, the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics is presented, which features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm2 6T-SRAM bit cell.
Patent
Deposition by adsorption under an electrical field
TL;DR: In this article, an electrical field is applied during the substrate exposing step to cause a reactive branch of the precursor molecules to adsorb into the surface of the substrate in a manner such that the precursors have essentially the same orientation.
Journal ArticleDOI
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below
Claire Fenouillet-Beranger,Stephane Denorme,Pierre Perreau,C. Buj,O. Faynot,Francois Andrieu,L. Tosti,Sébastien Barnola,T. Salvetat,X. Garros,Mikael Casse,F. Allain,Nicolas Loubet,Loan Pham-Nguyen,E. Deloffre,Mickael Gros-Jean,Remi Beneyton,C. Laviron,M. Marin,C. Leyris,Sebastien Haendler,Francois Leverd,Pascal Gouraud,P. Scheiblin,L. Clement,Roland Pantel,Simon Deleonibus,Thomas Skotnicki +27 more
TL;DR: In this article, the authors compared Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP) conditions and compared them with bulk 45-nm technology in terms of variability and noise.
Journal ArticleDOI
In situ electric field simulation in metal/insulator/metal capacitors
TL;DR: In this paper, the effect of interface topography on metal/insulator/metal (MIM) capacitor electrical properties was analyzed by numerical simulations of the electric field established in a MIM structure with a 45nm thick Ta2O5 film.
Proceedings ArticleDOI
Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
Claire Fenouillet-Beranger,Pierre Perreau,Loan Pham-Nguyen,Stephane Denorme,Francois Andrieu,L. Tosti,L. Brevard,Olivier Weber,Sébastien Barnola,T. Salvetat,X. Garros,Mikael Casse,Charles Leroux,Jean-Philippe Noel,Olivier P. Thomas,B. Le-Gratiet,F. Baron,Maxime Gatefait,Yves Campidelli,F. Abbate,C. Perrot,C. De-Buttet,Remi Beneyton,L. Pinzelli,Francois Leverd,Pascal Gouraud,Mickael Gros-Jean,A. Bajolet,Cecilia M. Mezzomo,C. Leyris,Sebastien Haendler,D. Noblet,R. Pantel,A. Margain,C. Borowiak,Emmanuel Josse,Nicolas Planes,D. Delprat,F. Boedt,K. Bourdelle,B.Y. Nguyen,Frederic Boeuf,O. Faynot,Thomas Skotnicki +43 more
TL;DR: In this article, the FD-SOI with High-K and Single Metal gate is presented as a possible candidate for LP multimedia technology, and a hybrid FDSOI/bulk co-integration with UTBOX is demonstrated for LP applications.