F. Abbate

TL;DR: A 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors using forward back bias is presented and it is experimentally demonstrated that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed.

TL;DR: For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated and the effectiveness of back biasing for short devices in order to achieve I-ON current improvement by 45% for LVT options at an I-OFF current of 23nA/µm and a leakage reduction by 2 decades.

TL;DR: In this article, the impact of an ultra-thin box (UTBOX) with and without ground plane (GP) on a 32-nm fully-depleted SOI (FDSOI) high-k/metal gate technology is explored.

TL;DR: The combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299µm2 SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.

TL;DR: In this article, the impact of an Ultra-Thin Box (UTBOX) with and without ground plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology is explored for the first time.