Drain Dielectric Pocket Engineering: its Impact on the Electrical Performance of a Hetero-Structure Tunnel FET

This article presented the first-ever 2D analytical model for the surface potential of dual material gate overlapped-on-drain TFET (DMG-TFET) device for label-free biosensor application using dielectric modulation technique. The use of two different metal work functions for the gate (ϕM1<ϕM2) impacts the device’s surface potential to increase tunneling width at the secondary tunneling junction to enhance the device sensitivity compared to single material gate device. This model takes into account the effect of changing the dielectric constant value, location, and percentage of fill factor of the target biomolecules on the surface potential of the device. The parabolic approximation of surface potential is used for solving the 2D-Poisson’s equation by applying suitable boundary conditions. The analytical surface potential results are verified with the simulation result using the SILVACO Atlas tool. 

Analytical modelling for Surface potential of Dual material gate overlapped-on-drain TFET(DM-DMG-TFET) for Label-free biosensing Application

This report presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.

A Physical Poly-Silicon Thin Film Transistor (TFT) Model for Circuit

In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (LGs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time ...

Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

An inner-gate engineered double gate heterostructure tunnel field effect transistor (SiGe/Si-IGTFET) has been presented. The inner-gate is grown at the center of the Si0.6Ge0.4/Si TFET, followed by a thin HfO2 dielectric layer. The drain current performance of the suggested device has been investigated comprehensively to discover its efficacy. The device provides much-lower ambipolarity (by 6 decades) compared to heterostructure TFET with a similar dimension. The SiGe/Si-IGTFET device has also shown higher immunity against short channel effects such as drain induced barrier lowering and gate induced drain leakage current (I GIDL). To examine the impact of inner-gate, various DC parameters such as ambipolar current (I amb), on current (I on), I on/I amb current ratio, average subthreshold swing (SS), surface potential, and electric field have been considered. The device offers a much improved current ratio (I on/I amb) of 1.78 × 1012 with an average SS of 23 mV decade−1 by optimizing the position and dielectric material of the inner-gate. The simulation of the suggested device is carried out using a 2D Silvaco Technology Computer-Aided Design (TCAD) device simulator.

Design and analysis of a double gate SiGe/Si tunnel FET with unique inner-gate engineering

In this work gate-on-drain L-shaped channel Tunnel FET is proposed to detect various biomolecules through label-free bio-sensing detection technique. Biomolecules can be detected in the proposed structure through modulation of ambipolar current between channel and drain. Modulation of ambipolar current is performed by extending gate over drain in order to create a gate to drain overlap (cavity) by etching the specific portion of the gate. Trapped biomolecules within cavity gets immobilized. Immobilized biomolecules change the drain to channel tunneling width, thus changing the ambiploar leakage current. Drain doping and cavity length was fine-tuned to achieve better sensitivity in terms of ambipolar current and ambipolar knee voltage shift with and without presence of biomolecules. A maximum sensitivity of 3.8 × 107 is achieved for drain doping of 5 × 1019 donors/cm3 and cavity length of 60 nm. A high value of sensitivity is achieved for each biomolecules when drain doping ranged from 1019 donors/cm3 to 5 × 1019 donors/cm3 and cavity length ranged between 40 nm to 50 nm. Effect of differently charged biomolecules on sensitivity has also be structured.

/pdf/gate-on-drain-overlapped-l-shaped-channel-tunnel-fet-as-1780ydvz3h.pdf

Gate-on-Drain Overlapped L-Shaped Channel Tunnel FET as Label-Free Biosensor

A compact model in MATLAB environment of amorphous silicon and polycrystalline silicon based thin film transistor is essential to all Active Matrix Organic LED (AMOLED) designers to assessing and envisaging the performance of AMOLED's. This model explains the three regions of thin film transistor operation, i.e. leakage region, sub threshold region and above threshold region. The proposed model shows good settlement with experimental data reported elsewhere. The polycrystalline silicon thin film transistor shows better electrical properties, such as, high relative ON/OFF ratio, high mobility, and low power consumption than amorphous silicon thin film transistor.

An efficient modelling of amorphous silicon and polycrystalline silicon thin film transistor for AMOLED display using MATLAB

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field (Eeff) on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be Eeff−1.8 and Eeff−2.4, respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of Eeff in controlling the value of channel mobility in 4H-SiC MOSFETs.

/pdf/study-of-carrier-mobilities-in-4h-sic-mosfets-using-hall-2ugl30o8.pdf

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis

In this article, for the first time, an asymmetric U-shaped-gated tunnel FET (AU-TFET), with a unique vertical channel epilayer, at sub-7-nm technology node, has been proposed and investigated for its suitability to be a universal device. After validating the simulation scheme with the experimental results of fabricated TFET devices, the impact of thickness of the said epilayer ( ${T}_{\text {epi}}$ ), on device performance, has been thoroughly investigated in terms of a variety of performance metrics, both in analog and digital (Ana–Digi) domains. To increase the vitality of the work, the device-level analysis is stretched to the circuit level. The impact on the inverter performance, both in Ana–Digi domains, in terms of fundamental circuit performance parameters, viz., dc gain, short-circuit power dissipation during switching, noise margin (NM), and so on, has been studied, and ultimately, the most optimized TFET structure, in each domain, has been identified. Finally, in this whole device/circuit co-analysis, after summing up all the performance metrics in both the domains while looking for meeting the low-power (LP) requirements (following the goals, as applicable, of international roadmaps), altogether, we have found that AU-TFET with ${T}_{\text {epi}} $ = 6 nm could be considered as the ultimate optimized universal LP Ana–Digi TFET structure.

Suman Das

Papers

Gate-on-Drain Overlapped L-Shaped Channel Tunnel FET as Label-Free Biosensor

Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

An efficient modelling of amorphous silicon and polycrystalline silicon thin film transistor for AMOLED display using MATLAB

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis

Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study