In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

https://www.silvaco.co.kr/tech_lib_TCAD/simulationstandard/2008/jan_feb_mar/a2/jan-feb-mar08_a2.pdf

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.

Multiple-gate SOI MOSFETs

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

/pdf/finfets-and-other-multi-gate-transistors-541arp307w.pdf

FinFETs and Other Multi-Gate Transistors

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Frontiers of silicon-on-insulator

This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Beyond the conventional transistor

The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.

Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance

A comprehensive investigation of edge effects in LOCOS-isolated silicon-on-insulator devices is made by combining the measurements of the static characteristics, charge pumping, and noise. Even when a substrate bias is used to mask the conduction on the island edges, the high-frequency edge effects are still detectable. Appropriate models are proposed to separate the edge contribution from those of the front and back interfaces. It is found that the defect density on the edges is inhomogeneous, increasing vertically from the top to the bottom of the film and laterally from the middle to the end of the channel. Slow traps are identified at the back interface, close to the source/drain junctions. >

Detailed analysis of edge effects in SIMOX-MOS transistors

https://ieeexplore.ieee.org/iel5/55/31993/01487227.pdf

le-Gate ilicon-on r Transistor with nversion: A evice with Grea

The extension of the charge pumping technique to gated P+ IN+ diodes fabricated on silicon on insulator is analysed. This method allows us to evaluate the interface properties in SOS and SIMOX structures, without the need for 5-terminal MOS transistors. The experiment, performed on SIMOX films by pulsing both the gate and substrate, reveal the existence of a high density of fast interface states and bulk traps near the buried oxide.

/pdf/charge-pumping-in-silicon-on-insulator-structures-using-n6d6t5rqiq.pdf

Charge Pumping in Silicon on Insulator Structures using Gated P-I-N Diodes

In this paper, we present new methods and results related to the characterization of silicon on insulator material fabricated by deep oxygen implantation (SIMOX). The minority carrier lifetime as well as the surface recombination velocity are obtained using depletion-mode MOSFETs. This is done by monitoring the drain current while the gate is being pulsed into deep depletion.

T. Elewa

Papers

Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance

Detailed analysis of edge effects in SIMOX-MOS transistors

le-Gate ilicon-on r Transistor with nversion: A evice with Grea

Charge Pumping in Silicon on Insulator Structures using Gated P-I-N Diodes

Interface Properties and Recombination Mechanisms in Simox Structures