As we move toward the commercialization of Spin-Transfer Torque Magnetic Random Access Memories (STT -MRAM), cost-effective testing and in-field reliability have become more prominent. Among STT-MRAM manufacturing defects, pinholes are one of the important ones. Pinholes are defects on the surface of the oxide layer which degrade the resistive values and, in some cases, cause an oxide breakdown. Some moderate levels of pinhole defects can remain undetected during standard functional tests and may cause a field failure. A stress test of the whole memory, including multiple cycles of long writes, has been suggested to detect candidate pinhole defects. However, this test not only causes extra costs but also degrades the reliability of MRAM for the entire array. In this paper, we have statistically studied the behavior of pinholes and proposed a cost-effective testing scheme to capture pinhole defects and increase the reliability of the end product. Our method limits the number of test candidate cells that need to be hammered, providing a reduced test time of up to 96.42% for our case studies compared to existing methods. This is while the advantages of standard tests are all preserved with our method. The proposed approach is compatible with memory-built-in self-test (MBIST) schemes.

Smart Hammering: A practical method of pinhole detection in MRAM memories

We have systematically investigated the reliability performance of spin-orbit torque (SOT) magnetic random access memory (MRAM) devices, including electromigration (EM), stress migration (SM), endurance and data retention. The results show that the SOT-MRAM devices pass the EM requirement over 10 years lifetime under the operation condition, and pass the SM requirement over 1000 hours baking at 175°C. Moreover, high endurance close to 1014 cycles and robust data retention over 10 years storage time were demonstrated for the same SOT-MRAM devices. This full characterization fills the blank of SOT-MRAM reliability research and would contribute to the commercialization of the SOT-MRAM.

Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays

We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet >1M cycles with solder reflows and path towards achieving >E12 cycles for cache applications.

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

Threshold voltage ( $\text{V}_{\text{TH}}$ ) needs to be well controlled to determine the switching point of the transistors However, $\text{V}_{\text{TH}}$ variation was observed on high voltage transistor during development phase Investigations show that the $\text{V}_{\text{TH}}$ variation was caused by phosphorus contamination from wafer backside Various wet chemical cleaning methods were evaluated to understand the effectiveness for the phosphorus decontamination Good $\text{V}_{\text{TH}}$ result was achieved with improved cleaning solution

Study for phosphorus contamination to high voltage transistors

STT-MRAM has been showcased to be a viable solution to replace eFlash and SRAM technologies. With the increasing demand for connected edge computing and internet of things, the usage of STT-MRAM in MCU and MPU products has become the reality. The product reliability of industrial-grade (-40~125°C) 40Mb 22FDX® embedded-MRAM technology having 5x-solder reflows compatibility stack is presented. The stand-by magnetic immunity and cross-talk between MRAM and RF are also discussed.

STT-MRAM Product Reliability and Cross-Talk

Volcano defect is found on non-volatile memory structure after tungsten contact formation, causing longer tungsten CMP polishing time, generation of dark voltage contrast defect under e-beam inspection and severely degraded product yield. The effects of ALD TiN and position of contact liner anneal are studied for defect reduction and yield improvement.

Tan Yun Ling

Papers

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

Study for phosphorus contamination to high voltage transistors

STT-MRAM Product Reliability and Cross-Talk

Volcano Defect Prevention in Tungsten Contact Formation for Embedded Non-volatile Memory