Real silicon reveals a lot about how new silicon processes work, so test chips are particularly helpful for the semiconductor manufacturers to evaluate a new technology. Traditionally, semiconductor manufacturers relied only on SRAM test chips for ramping up, qualifying and monitoring new semiconductor fabrication processes. Unfortunately, the transistor and circuit geometries used in an SRAM test chip represent only a small fraction of the transistor and circuit geometries found in a real product [BHA98]. In recent years, logic test chip that narrows the gap between the SRAM chips and the real products are used extensively [BHA98] [HES07] [KAR08]. The logic test vehicle is more representative of real product, but may not be as easily testable and diagnosable as the SRAMs. The logic test chips must capture information related to device and interconnect variability, including systematic and random variations, as well as manufacturing features used in lithography, thermal, stress, proximity effects, and they must use all potentially to-be-used library cells. The logic test chips will help manufacture to incorporate silicon-accurate models and enhanced the manufacturing process. In the past, logic test chips are a small function design that contains as more manufacturing features as possible. As for the test chips, the functionality of a chip does not matter. It is required that the test chip must be designed to cover all manufacturing features. It would be feasible if we can design a test chip with many scan cells such that each scan cell contains some manufacturing features to be used, and all scan cells cover all manufacturing features. Testing such a test chip becomes testing all scan cells and their interconnections. In case a failure occurs, diagnosis down to a scan cell can be easily achieved if we use some special scan architectures. In this paper we present the concept of a two-dimensional scan architecture that makes testing and diagnose down to defective scan cells more easily.

On designing two-dimensional scan architecture for test chips

This paper discusses application of direct charge measurement (DCM) on characterizing on-chip interconnect capacitance. Measurement equipment and techniques are leveraged from Flat Panel Display testing. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. Femto-Farad measurement sensitivity is achieved without having on-chip active device. Measurement results of silicon and glass substrates, including parallel measurements, are presented.

Benefit of Direct Charge Measurement (DCM) on Interconnect Capacitance Measurement

Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.

Two-Dimensional Scan Architecture

For advanced technologies, the current industry is seeing very complicated silicon defect types and defect distribution. It is very common for the yield of a new design with new technology to start at a very low level and it's critical to ramp up yield as quickly as possible to meet the market window. We propose to use special scan chain test patterns to take advantage special scan chain architecture proposed before. These patterns can achieve perfect diagnostic resolution and hence help to ramp up yield quickly.

Reversible Scan Based Diagnostic Patterns

We describe the development and use of various test structures for 32nm yield enhancement. These DC defect test structures are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards. This new test method provides measurement accuracy as high as ± 10 pA along with up to 9x reduction in test time over conventional parametric testing. The large critical area enables reliable estimation of defect densities by failure mechanism.

Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement

A comprehensive 45 nm short-flow test chip was designed and is currently used to improve defect-limited yield. In a novel development to reduce test time, the DC test structures are tested in parallel mode on a functional test platform, resulting in a 5x reduction in test time over conventional parametric testing. The large critical area enables accurate measurement of defect densities down to the ppb-level, while the reduced cycle time of this short-flow test chip makes it an excellent routine defect monitor as well as a test vehicle for evaluating process changes.

Short-flow test chip utilizing fast testing for defect density monitoring in 45nm

We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet >1M cycles with solder reflows and path towards achieving >E12 cycles for cache applications.

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

Embedded STT-MRAM has emerged to high-volume ramp stage. To sustain yield and to guarantee reliable operation of the memory arrays, a solid line of defense strategy is required. The unprecedented complexity of the MTJ, acting as the memory element in this new technology, can be compensated by an equally unprecedented reservoir of versatile characterization methodologies allowing for the prediction of yield and reliability critical properties of the final memory cell. To enhance the turnaround time of tool monitoring and to enable fast film level and patterned MTJ metrology, the transition of classical lab-based methodologies, such as perpendicular magneto-optical Kerr effect, current-in-plane tunneling and ferromagnetic resonance, to full on-chip capability is essential. The complementary use of these magneto-electrical and magneto-optical techniques for drift partitioning as well as their correlation to the final wafer electrical test and reliability are key for establishing a strong line of defense.

From Emergence to Prevalence: 22FDX® Embedded STT-MRAM

STT-MRAM has been showcased to be a viable solution to replace eFlash and SRAM technologies. With the increasing demand for connected edge computing and internet of things, the usage of STT-MRAM in MCU and MPU products has become the reality. The product reliability of industrial-grade (-40~125°C) 40Mb 22FDX® embedded-MRAM technology having 5x-solder reflows compatibility stack is presented. The stand-by magnetic immunity and cross-talk between MRAM and RF are also discussed.

T. Merbeth

Papers

Short-flow test chip utilizing fast testing for defect density monitoring in 45nm

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

From Emergence to Prevalence: 22FDX® Embedded STT-MRAM

STT-MRAM Product Reliability and Cross-Talk