We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet >1M cycles with solder reflows and path towards achieving >E12 cycles for cache applications.

As we move toward the commercialization of Spin-Transfer Torque Magnetic Random Access Memories (STT -MRAM), cost-effective testing and in-field reliability have become more prominent. Among STT-MRAM manufacturing defects, pinholes are one of the important ones. Pinholes are defects on the surface of the oxide layer which degrade the resistive values and, in some cases, cause an oxide breakdown. Some moderate levels of pinhole defects can remain undetected during standard functional tests and may cause a field failure. A stress test of the whole memory, including multiple cycles of long writes, has been suggested to detect candidate pinhole defects. However, this test not only causes extra costs but also degrades the reliability of MRAM for the entire array. In this paper, we have statistically studied the behavior of pinholes and proposed a cost-effective testing scheme to capture pinhole defects and increase the reliability of the end product. Our method limits the number of test candidate cells that need to be hammered, providing a reduced test time of up to 96.42% for our case studies compared to existing methods. This is while the advantages of standard tests are all preserved with our method. The proposed approach is compatible with memory-built-in self-test (MBIST) schemes.

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

Smart Hammering: A practical method of pinhole detection in MRAM memories

We have systematically investigated the reliability performance of spin-orbit torque (SOT) magnetic random access memory (MRAM) devices, including electromigration (EM), stress migration (SM), endurance and data retention. The results show that the SOT-MRAM devices pass the EM requirement over 10 years lifetime under the operation condition, and pass the SM requirement over 1000 hours baking at 175°C. Moreover, high endurance close to 1014 cycles and robust data retention over 10 years storage time were demonstrated for the same SOT-MRAM devices. This full characterization fills the blank of SOT-MRAM reliability research and would contribute to the commercialization of the SOT-MRAM.

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

Citations

Smart Hammering: A practical method of pinhole detection in MRAM memories

Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays