This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At the microarchitectural level, McPAT includes models for the fundamental components of a chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, integrated memory controllers, and multiple-domain clocking. At the circuit and technology levels, McPAT supports critical-path timing modeling, area modeling, and dynamic, short-circuit, and leakage power modeling for each of the device types forecast in the ITRS roadmap including bulk CMOS, SOI, and double-gate transistors. McPAT has a flexible XML interface to facilitate its use with many performance simulators. Combined with a performance simulator, McPAT enables architects to consistently quantify the cost of new ideas and assess tradeoffs of different architectures using new metrics like energy-delay-area2 product (EDA2P) and energy-delay-area product (EDAP). This paper explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting tradeoffs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies of cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks at the 22nm technology node for both common in-order and out-of-order manycore designs shows that when die cost is not taken into account clustering 8 cores together gives the best energy-delay product, whereas when cost is taken into account configuring clusters with 4 cores gives the best EDA2P and EDAP.

/pdf/mcpat-an-integrated-power-area-and-timing-modeling-framework-38b785sayc.pdf

McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures

Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.

/pdf/parameter-variations-and-impact-on-circuits-and-k3j22hqcec.pdf

Parameter variations and impact on circuits and microarchitecture

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.

http://www.ee.unlv.edu/~meiyang/ecg700/readings/Thousand%20Core%20Chips%20A%20Technology%20Perspective.pdf

Thousand core chips: a technology perspective

This paper presents a new multiresonant frequency-adaptive synchronization method for grid-connected power converters that allows estimating not only the positive- and negative-sequence components of the power signal at the fundamental frequency but also other sequence components at other harmonic frequencies. The proposed system is called MSOGI-FLL since it is based on both a harmonic decoupling network consisting of multiple second-order generalized integrators (MSOGIs) and a frequency-locked loop (FLL), which makes the system frequency adaptive. In this paper, the MSOGI-FLL is analyzed for single- and three-phase applications, deducing some key expressions regarding its stability and tuning. Moreover, the performance of the MSOGI-FLL is evaluated by both simulations and experiments to show its capability for detecting different harmonic components in a highly polluted grid scenario.

/pdf/multiresonant-frequency-locked-loop-for-grid-synchronization-1b1w90po2u.pdf

Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.

Area-efficient linear regulator with ultra-fast load regulation

A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (V CC ) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal V CC or at least 17% V CC reduction at equal throughput, corresponding to 31%-37% total power reduction.

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal VCC or at least 17% VCC reduction at equal throughput, corresponding to 31%-37% total power reduction.

A comparison of on-chip inductors with magnetic materials from previous studies is presented and examined. Results from on-chip inductors with magnetic material integrated into a 90 nm CMOS processes are presented. The inductors use copper metallization and amorphous Co-Zr-Ta magnetic material. Inductance densities of up to 1700 nH/mm2 were obtained thanks to inductance increases of up to 31 times, significantly greater than previously published on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. Co-Zr-Ta was chosen for its good combination of high permeability, good stability at high temperature (> 250degC), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The Co-Zr-Ta alloy can operate at frequencies up to 9.8 GHz, but trade-offs exist between frequency, inductance, and quality factor. Our inductors with thick copper and thicker magnetic films have dc resistances as low as 0.04 Omega, and quality factors of up to 8 at frequencies as low as 40 MHz.

Tanay Karnik

Papers

Parameter variations and impact on circuits and microarchitecture

Area-efficient linear regulator with ultra-fast load regulation

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

Review of On-Chip Inductor Structures With Magnetic Films