Journal ArticleDOI
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
Keith Bowman,James W. Tschanz,Nam Sung Kim,Janice C. Lee,Christopher B. Wilkerson,Shih-Lien Lu,Tanay Karnik,Vivek De +7 more
TLDR
In this article, a 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path activation probabilities for maximizing throughput.Abstract:
A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal VCC or at least 17% VCC reduction at equal throughput, corresponding to 31%-37% total power reduction.read more
Citations
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Journal ArticleDOI
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial
TL;DR: It is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect and common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.
Journal ArticleDOI
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
Keith Bowman,J. Tschanz,Shih-Lien Lu,Paolo Aseron,Muhammad M. Khellah,Arijit Raychowdhury,Bibiche M. Geuskens,Carlos Tokunaga,Christopher B. Wilkerson,Tanay Karnik,Vivek De +10 more
TL;DR: While core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (VCC) measurements.
Journal ArticleDOI
Correction to “A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation”
David Michael Bull,Shidhartha Das,Karthik Shivashankar,Ganesh Dasika,Krisztian Flautner,David Blaauw +5 more
TL;DR: This paper applies Razor to a 32 bit ARM processor with a micro-architecture design that has balanced pipeline stages with critical memory access and clock-gating enable paths, and shows potential for parametric yield improvement through energy-efficient operation using Razor.
Journal ArticleDOI
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction
Matthew Fojtik,David Fick,Yejoong Kim,Nathaniel Pinckney,David Harris,David Blaauw,Dennis Sylvester +6 more
TL;DR: B Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows is proposed and implemented on an ARM Cortex-M3 microprocessor in 45 nm CMOS to demonstrate the technique's automated capability.
Journal ArticleDOI
Underdesigned and Opportunistic Computing in Presence of Hardware Variability
Puneet Gupta,Yuvraj Agarwal,Lara Dolecek,Nikil Dutt,Rajesh Gupta,Rakesh Kumar,Subhasish Mitra,Alexandru Nicolau,Tajana Rosing,Mani Srivastava,Steven Swanson,Dennis Sylvester +11 more
TL;DR: Specific sensing mechanisms that have been developed and their potential use in building underdesigned and opportunistic computing machines, including software stack that opportunistically adapts to a sensed or modeled hardware.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Book
Computer Architecture: A Quantitative Approach, 2nd Edition
TL;DR: A quantitative approach to computer architecture a quantitative approach 5th edition computer architecture quantitative approach solution manual computer Architecture quantitative approach solutions manual computer architecture an quantitative approach 3rd editionComputer architecture, fifth edition.
Proceedings ArticleDOI
Razor: a low-power pipeline based on circuit-level timing speculation
Daniel J. Ernst,Nam Sung Kim,Shidhartha Das,Sanjay Pant,Rajeev R. Rao,Toan Pham,Conrad H. Ziesler,David Blaauw,Todd Austin,Krisztian Flautner,Trevor Mudge +10 more
TL;DR: A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.
Proceedings ArticleDOI
Time redundancy based soft-error tolerance to rescue nanometer technologies
TL;DR: This work uses time redundancy techniques to derive low cost soft-error tolerant implementations for logic networks in response to the increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling.
Proceedings ArticleDOI
Circuit Failure Prediction and Its Application to Transistor Aging
TL;DR: Simulation results using 90nm and 65nm technologies demonstrate that a new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost and can significantly improve system performance by enabling close to best- case design instead of traditional worst-case design.