Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

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Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Substantial effort has been placed on developing semiconducting carbon nanotubes and nanowires as building blocks for electronic devices--such as field-effect transistors--that could replace conventional silicon transistors in hybrid electronics or lead to stand-alone nanosystems. Attaching electric contacts to individual devices is a first step towards integration, and this step has been addressed using lithographically defined metal electrodes. Yet, these metal contacts define a size scale that is much larger than the nanometre-scale building blocks, thus limiting many potential advantages. Here we report an integrated contact and interconnection solution that overcomes this size constraint through selective transformation of silicon nanowires into metallic nickel silicide (NiSi) nanowires. Electrical measurements show that the single crystal nickel silicide nanowires have ideal resistivities of about 10 microOmega cm and remarkably high failure-current densities, >10(8) A cm(-2). In addition, we demonstrate the fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal-semiconductor interfaces. We produce field-effect transistors based on those heterostructures in which the source-drain contacts are defined by the metallic NiSi nanowire regions. Our approach is fully compatible with conventional planar silicon electronics and extendable to the 10-nm scale using a crossed-nanowire architecture.

Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures

High performance digital-analog mixed devices are fabricated on a high resistivity MCZ Si substrate with low oxygen in order to suppress substrate noise from digital to analog circuits The low oxygen prevents substrate resistivity reduction due to thermal donor occurring during device fabrication process Good characteristics of digital, analog and power amplifiers can be realized by optimizing the process of oxynitride, halo implantation and salicide In 011 /spl mu/m CMOS, high drivability, that is, 770 /spl mu/A//spl mu/m for NMOS and 330 /spl mu/A//spl mu/m for PMOS was achieved at Ioff=10/sup -9/ A//spl mu/m And fT value of 90 GHz for NMOS and 48 GHz for PMOS can be achieved Additionally, high efficiency of 68% at 2 GHz operation can be realized in power amplifier with 030 /spl mu/m gate length

High performance digital-analog mixed device on an Si substrate with resistivity beyond 1 k/spl Omega/ cm

A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.

Semiconductor device comprising plurality of semiconductor areas having the same top surface and different film thicknesses and manufacturing method for the same

A contact filling-technique that utilizes polysilicon plug formation followed by Ni silicidation with a TiN barrier at the polysilicon plug bottom is described. Self-aligned complete silicidation of both shallow and deep contacts can be achieved at the same time by using the TiN silicidation stop. By using this technique in place of a polysilicon plug, low contact resistance was achieved for both n/sup +/ and p/sup +/ contacts. A completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicide plug demonstrate the integrity of the technique. >

A novel selective Ni/sub 3/Si contact plug technique for deep-submicron ULSIs

A contact plug technique employing selective nickel silicidation of polysilicon with a titanium nitride barrier layer has been developed. This technique provides a contact resistance equal to that of an unplugged metal contact, while also realizing the flatness of a polysilicon plug over contact regions. Using this technique, a completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The structure of the plug was analyzed using TEM photography, EDX, and electro-diffraction measurements, and the silicidation stopping ability of the TiN layer was confirmed. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicided plug are demonstrations of the integrity of this technique. The results indicate that this technology is suitable for deep-submicrometer ULSIs. >

A new contact plug technique for deep-submicrometer ULSI is employing selective nickel silcidation of polysilicon with a titanium nitride stopper

With the expected limitations of conventional CMOS downsizing, various new structures, such as vertical and concave MOSFETs, are under serious investigation. These new types of MOSFETs have a special feature in that the channel of the MOSFETs consists of various surfaces with different crystal orientations. With thinning of the gate oxides, the substrate orientation dependence of the oxide quality becomes a major concern, because Si-SiO/sub 2/ interface quality control becomes important in terms of suppressing the tunneling leakage current and improving TDDB reliability (Sorsch et al., 1998). This paper, for the first time, reports the surface orientation dependence of the ultra-thin gate oxide properties in the direct tunneling regime. Various characteristics of the oxide and MOSFET properties were compared by fabricating direct-tunneling gate CMOS on [100]-, [100] 4/spl deg/off, and [111]-oriented Si substrates.

https://www.vlsisymposium.org/Past/01web/technology/tec_pdf/T7Ap1.pdf

Tatsuya Ohguro

Papers

High performance digital-analog mixed device on an Si substrate with resistivity beyond 1 k/spl Omega/ cm

Semiconductor device comprising plurality of semiconductor areas having the same top surface and different film thicknesses and manufacturing method for the same

A novel selective Ni/sub 3/Si contact plug technique for deep-submicron ULSIs

A new contact plug technique for deep-submicrometer ULSI is employing selective nickel silcidation of polysilicon with a titanium nitride stopper

Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide