This paper proposes a synthesis of different electrical methods used to estimate the temperature of power semiconductor devices. The following measurement methods are introduced: the voltage under low current levels, the threshold voltage, the voltage under high current levels, the gate-emitter voltage, the saturation current, and the switching times. All these methods are then compared in terms of sensitivity, linearity, accuracy, genericity, calibration needs, and possibility of characterizing the thermal impedance or the temperature during the operation of the converter. The measurement of thermo-sensitive parameters of wide bandgap semiconductors is also discussed.

/pdf/temperature-measurement-of-power-semiconductor-devices-by-1nz3bww95c.pdf

Temperature Measurement of Power Semiconductor Devices by Thermo-Sensitive Electrical Parameters—A Review

The introduction of enhancement-mode gallium-nitride-based power devices such as the eGaN FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the printed circuit board (PCB) layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET-based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This paper will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design, providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Understanding the Effect of PCB Layout on Circuit Performance in a High-Frequency Gallium-Nitride-Based Point of Load Converter

The introduction of enhancement mode gallium nitride based power devices such as the eGaN®FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with Silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the PCB layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This work will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter

This article reviews the design and evaluation of different DC-DC converter topologies for Battery Electric Vehicles (BEVs) and Plug-in Hybrid Electric Vehicles (PHEVs). The design and evaluation of these converter topologies are presented, analyzed and compared in terms of output power, component count, switching frequency, electromagnetic interference (EMI), losses, effectiveness, reliability and cost. This paper also evaluates the architecture, merits and demerits of converter topologies (AC-DC and DC-DC) for Fast Charging Stations (FCHARs). On the basis of this analysis, it has found that the Multidevice Interleaved DC-DC Bidirectional Converter (MDIBC) is the most suitable topology for high-power BEVs and PHEVs (> 10kW), thanks to its low input current ripples, low output voltage ripples, low electromagnetic interference, bidirectionality, high efficiency and high reliability. In contrast, for low-power electric vehicles (<10 kW), it is tough to recommend a single candidate that is the best in all possible aspects. However, the Sinusoidal Amplitude Converter, the Z-Source DC-DC converter and the boost DC-DC converter with resonant circuit are more suitable for low-power BEVs and PHEVs because of their soft switching, noise-free operation, low switching loss and high efficiency. Finally, this paper explores the opportunity of using wide band gap semiconductors (WBGSs) in DC-DC converters for BEVs, PHEVs and converters for FCHARs. Specifically, the future roadmap of research for WBGSs, modeling of emerging topologies and design techniques of the control system for BEV and PHEV powertrains are also presented in detail, which will certainly help researchers and solution engineers of automotive industries to select the suitable converter topology to achieve the growth of projected power density.

DC-DC Converter Topologies for Electric Vehicles, Plug-in Hybrid Electric Vehicles and Fast Charging Stations: State of the Art and Future Trends

This paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum dead-time controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.

https://ir.nctu.edu.tw:443/bitstream/11536/10158/1/000250524500015.pdf

Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications

This paper presents a 4 MHz, 0.9 W digitally controlled DC-DC converter with a miniature planar inductor for 1.8 V portable devices. In applications such as cellular phones, it is crucial to achieve high conversion efficiency over the entire load range. A binary-weighted segmented power stage is used to dynamically optimize the converter efficiency by reducing the gate-drive losses at mid-to-light loads. An all-digital segment controller based on a load current estimator is demonstrated. This approach is most effective in the mid-load range, where the losses are reduced by 33 %, corresponding to an efficiency improvement of 7.5 % at V in = 4.2 V. A peak efficiency of 89 % is achieved at f s = 4 MHz and V in = 2.7 V.

A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency

A system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators. The SiP offers the world's lowest power dissipation of 3.8 W at 1 MHz. Its parasitic inductance is 44% lower than SiPs with the input capacitor mounted on the PCB, due to a small loop from the input capacitor to the MOSFETs, which reduces power dissipation by 25% at the same peak voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the MOSFET to the input capacitor. The lead frames and MOSFETs are connected with Cu leads, which reduce the spreading resistance of the MOSFET electrodes.

System in package with mounted capacitor for reduced parasitic inductance in voltage regulators

In this paper, a segmented IGBT gate driver IC for mitigating IGBT turn-on IC over-shoot is presented. The proposed IC is fabricated using TSMC's 0.18 μm BCD Gen-2 process. Unlike existing IC over-shoot reduction techniques, the proposed technique does not require significant additional external components or an increase in turn-on energy. During turn-on, the gate driver is controlled such that (dVGE/dt) is kept low as current is transferred from the FWD to the IGBT and kept high at all other times. The ideal timing of (dVGE/dt) transitions could vary between IGBT devices, age, temperature, etc. A feedback system is used to correct for these variances. A 37% reduction in IC overshoot is achieved while maintaining the same EON. A 54% reduction in EON is achieved for the same IC overshoot. Finally, a 15.5 dBm reduction in CEMI is observed when compared to operation with a constant ROUT and similar Eon.

A segmented gate driver IC for the reduction of IGBT collector current over-shoot at turn-on

This paper presents a system-in-package (SiP) that mounts an input capacitor for voltage regulators. The SiP has a low power loss of 3.8 W at a switching frequency of 1 MHz, input voltage of 12 V, and output current of 25 A. The parasitic inductance of this SiP is 56% that of the previously reported SiP, which had the input capacitor mounted on the printed circuit board, and this reduction is due to the short current loop from the input capacitor to the MOSFETs. As a result, the power loss can be reduced by 20% for the same spike voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the drain electrode of the high-side MOSFET and the source electrode of the low-side MOSFET to the mounted input capacitor. The authors also propose a way to estimate the parasitic inductance experimentally, not from a current measurement such as with a shunt resistor and a current probe, but from the ringing frequency when the high-side MOSFET is switched and the output capacitance C oss of the MOSFET being on the off state.

A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

Conventional insulated gate bipolar transistor (IGBT) current sensing and protection techniques usually employ discrete sensors, such as lossy shunt resistors, and may involve accessing the high-voltage collector load of the IGBT. This would normally present difficulties for integration. This paper presents an IGBT gate driver IC with a collector current sensing circuit and an on-chip CPU for local data processing. This IC is prototyped using a TSMC 0.18 μm 40 V BCD Gen-2 process. The collector current sensing technique is based on the unique Miller plateau relationship between the gate current and collector current ( $I_{C}$ and $I_{G}$ ) for a particular gate resistance ( $R_{G}$ ). It allows a cycle-by-cycle measurement of IC during both turn- on and turn- off transients without any extra discrete components. The temperature variation is compensated internally by the on-chip CPU using polynomial curve fitting. This technique only monitors the low-voltage signal at the gate terminal, without the need to handle any high-voltage signal on the collector/load side. Measurements using a double pulse test setup show an accuracy of ±0.5 A over the current ranges of 1–30 A for turn- on and 1–50 A for turn- off from 25 to 75 °C.

/pdf/a-smart-igbt-gate-driver-ic-with-temperature-compensated-3hlw171l2t.pdf

Tetsuya Kawashima

Papers

A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency

System in package with mounted capacitor for reduced parasitic inductance in voltage regulators

A segmented gate driver IC for the reduction of IGBT collector current over-shoot at turn-on

A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

A Smart IGBT Gate Driver IC With Temperature Compensated Collector Current Sensing