Achieving high sensitivity in solid-state gas sensors can allow the precise detection of chemical agents. In particular, detection of volatile organic compounds (VOCs) at the parts per billion (ppb) level is critical for the early diagnosis of diseases. To obtain high sensitivity, two requirements need to be simultaneously satisfied: (i) low electrical noise and (ii) strong signal, which existing sensor materials cannot meet. Here, we demonstrate that 2D metal carbide MXenes, which possess high metallic conductivity for low noise and a fully functionalized surface for a strong signal, greatly outperform the sensitivity of conventional semiconductor channel materials. Ti3C2Tx MXene gas sensors exhibited a very low limit of detection of 50–100 ppb for VOC gases at room temperature. Also, the extremely low noise led to a signal-to-noise ratio 2 orders of magnitude higher than that of other 2D materials, surpassing the best sensors known. Our results provide insight in utilizing highly functionalized metallic...

Metallic Ti3C2Tx MXene Gas Sensors with Ultrahigh Signal-to-Noise Ratio

The Wigner function was formulated in 1932 by Eugene Paul Wigner, at a time when quantum mechanics was in its infancy. In doing so, he brought phase space representations into quantum mechanics. However, its unique nature also made it very interesting for classical approaches and for identifying the deviations from classical behavior and the entanglement that can occur in quantum systems. What stands out, though, is the feature to experimentally reconstruct the Wigner function, which provides far more information on the system than can be obtained by any other quantum approach. This feature is particularly important for the field of quantum information processing and quantum physics. However, the Wigner function finds wide-ranging use cases in other dominant and highly active fields as well, such as in quantum electronics—to model the electron transport, in quantum chemistry—to calculate the static and dynamical properties of many-body quantum systems, and in signal processing—to investigate waves passing through certain media. What is peculiar in recent years is a strong increase in applying it: Although originally formulated 86 years ago, only today the full potential of the Wigner function—both in ability and diversity—begins to surface. This review, as well as a growing, dedicated Wigner community, is a testament to this development and gives a broad and concise overview of recent advancements in different fields.

Recent advances in Wigner function approaches

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

Recently, ferroelectric tunnel junctions have attracted much attention due to their potential applications in non-destructive readout non-volatile memories. Using a semiconductor electrode has been proven effective to enhance the tunnelling electroresistance in ferroelectric tunnel junctions. Here we report a systematic investigation on electroresistance of Pt/BaTiO3/Nb:SrTiO3 metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier on Nb:SrTiO3 surface via varying BaTiO3 thickness and Nb doping concentration. The optimum ON/OFF ratio as great as 6.0 × 106, comparable to that of commercial Flash memories, is achieved in a device with 0.1 wt% Nb concentration and a 4-unit-cell-thick BaTiO3 barrier. With this thinnest BaTiO3 barrier, which shows a negligible resistance to the tunnelling current but is still ferroelectric, the device is reduced to a polarization-modulated metal/semiconductor Schottky junction that exhibits a more efficient control on the tunnelling resistance to produce the giant electroresistance observed. These results may facilitate the design of high performance non-volatile resistive memories.

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Giant tunnelling electroresistance in metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier

Recently, ferroelectric tunnel junctions (FTJs) have attracted considerable attention for potential applications in next-generation memories, owing to attractive advantages such as high-density of data storage, nondestructive readout, fast write/read access, and low energy consumption. Herein, recent progress regarding FTJ devices is reviewed with an emphasis on the modulation of the potential barrier. Electronic and ionic approaches that modulate the ferroelectric barriers themselves and/or induce extra barriers in electrodes or at ferroelectric/electrode interfaces are discussed with the enhancement of memory performance. Emerging physics, such as nanoscale ferroelectricity, resonant tunneling, and interfacial metallization, and the applications of FTJs in nonvolatile data storage, neuromorphic synapse emulation, and electromagnetic multistate memory are summarized. Finally, challenges and perspectives of FTJ devices are underlined.

Ferroelectric Tunnel Junctions: Modulations on the Potential Barrier

A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is...

A Vertically Integrated Junctionless Nanowire Transistor

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Vertically Integrated Multiple Nanowire Field Effect Transistor.

Through the characterization of a fabricated PIN diode with the aid of a simulation, a structural guideline for a reconfigurable antenna is developed. By comparing the conductivity with the equivalently normalized power, an optimal intrinsic channel length is determined. Simulation data show that a high carrier concentration is sustained along both the vertical and lateral directions in the intrinsic region. Due to the simple fabrication process and the controllability of the exposed channel region as well as the high carrier concentration with good uniformity, the proposed PIN diode is a viable candidate for a future antenna.

Optimization of the intrinsic length of a PIN diode for a reconfigurable antenna

Device degradation induced by hot-carrier injection was repaired by electrical annealing using Joule heat through a built-in heater in a gate. The concentrated high temperature anneals the gate oxide locally and the degraded device parameters are recovered or further enhanced within a short time of 1 ms. Selecting a proper range of repair voltage is very important to maximize the annealing effects and minimize the extra damages caused by excessive high temperature. The repairing voltage is related to the resistance of the poly-Si gate according to the device scaling.

Tewook Bang

Papers

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

A Vertically Integrated Junctionless Nanowire Transistor

Vertically Integrated Multiple Nanowire Field Effect Transistor.

Optimization of the intrinsic length of a PIN diode for a reconfigurable antenna

Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced From Hot-Carrier Injection