An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Data movement between the processing units and the memory in traditional von Neumann architecture is creating the “memory wall” problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the first one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite.To address the challenge, we propose DRISA, a DRAM-based Reconfigurable In-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be reconfigured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate significant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8× speedup and 1.2× better energy efficiency compared with ASICs, and 7.7× speedup and 15× better energy efficiency over GPUs with integer operations.CCS CONCEPTS• Hardware → Dynamic memory; • Computer systems organization → reconfigurable computing; Neural networks;

DRISA: a DRAM-based Reconfigurable In-Situ Accelerator

In one embodiment, a conductive interconnect ( 38 ) is formed in a semiconductor device by depositing a dielectric layer ( 28 ) on a semiconductor substrate ( 10 ). The dielectric layer ( 28 ) is then patterned to form an interconnect opening ( 29 ). A tantalum nitride barrier layer ( 30 ) is then formed within the interconnect opening ( 29 ). A catalytic layer ( 31 ) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer ( 30 ). A layer of electroless copper ( 32 ) is then deposited on the catalytic layer ( 31 ). A layer of electroplated copper ( 34 ) is then formed on the electroless copper layer ( 32 ), and the electroless copper layer ( 32 ) serves as a seed layer for the electroplated copper layer ( 34 ). Portions of the electroplated copper layer ( 34 ) are then removed to form a copper interconnect ( 38 ) within the interconnect opening ( 29 ).

Interconnect structure in a semiconductor device and method of formation

A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Microelectronic substrates with integrated devices

A wired circuit board has a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and having a pair of wires arranged in spaced-apart relation, and a semiconductive layer formed on the insulating layer and electrically connected to the metal supporting board and the conductive pattern The conductive pattern has a first region in which a distance between the pair of wires is small and a second region in which the distance between the pair of wires is larger than that in the first region The semiconductive layer is provided in the second region

Wired circuit board

A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and routing out a preselected portion of the base member to form an aperture. Metallization of the dielectric member and the walls of the aperture then occurs, followed by circuitization of the surfaces of the dielectric member. Direct metallization of the aperture walls eliminates many manufacturing steps previously required to metallize the aperture walls.

Method of making a circuitized substrate with an aperture

The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.

Method for reducing seed deposition in electroless plating

A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, C 30 H 50 O 10 , an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.

Colloidal seed formation for printed circuit board metallization

A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.

Method of making circuitized substrate with solder paste connections

The present invention comprises a method of making a circuitized structure. The method comprises the steps of providing a substrate coated with a polymeric dielectric layer, treating the substrate with alkali, baking the substrate to modify the surface of the polymeric dielectric layer, applying a seed layer to the polymeric dielectric layer and applying a conductive layer to the seed layer. The invention also comprises a printed circuit structure produced by the method of the present invention.

Thomas R. Miller

Papers

Method of making a circuitized substrate with an aperture

Method for reducing seed deposition in electroless plating

Colloidal seed formation for printed circuit board metallization

Method of making circuitized substrate with solder paste connections

Method of uniformly depositing seed and a conductor and the resultant printed circuit structure